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DDR SDRAM Memory Bank

Posted by InvisibleMan, 28 September 2011 - - - - - - · 32 views

Because I'm getting into the section on memory (and some parts of yesterday's example made me curious, particularly the RAS-to-CAS delay) I have decided to research RAM again. I did quite a bit of research in this area about a month ago, so a lot of this is review and should go by relatively quickly.

Data is stored in RAM in an array of...


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Memory Access Latency

Posted by InvisibleMan, 27 September 2011 - - - - - - · 25 views

A predicated instruction is an instruction whose execution depends on the result of a true/false test. Another way to look at it is a single instruction for code like the following:

if (a > b) c = 6;

Predicated instructions can help to reduce the number of branches in your code, which may increase how fast your...


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VLIW and Researching Interlocks

Posted by InvisibleMan, 27 September 2011 - - - - - - · 21 views

Trying out a different work schedule, so my blog entries may be a little erratic while I work out some of the kinks. So anyways, this blog post is for yesterday.

Today I learned about a couple new techniques. The first one is something called "very long instruction word" (VLIW). In VLIW, a single instruction is actually composed of...


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Instruction Throughput Decides All

Posted by InvisibleMan, 20 September 2011 - - - - - - · 11 views

I finally have an answer to my question! PleasingFungus from the #tigIRC channel on Esper discussed the question with me for two hours straight today and this is the answer I ended up with:

If a scalar (not superscalar) processor has multiple nonredundant functional units (a single FPU and a single ALU for example) and it issues an instruction...


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Scalar But Multiple Functional Units?

Posted by InvisibleMan, 19 September 2011 - - - - - - · 17 views

I spent most of the day trying to find the answer to the following question:

If a scalar (not superscalar) processor has multiple nonredundant functional units (a single FPU and a single ALU for example) and it issues an instruction to the FPU at a certain clock tick, could it issue another instruction to the ALU at the next clock tick so that both the ...






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