Memory data hazards are prevented by keeping a list of all the addresses with outstanding stores, and putting a load into a queue if it is for an address in that list. I don't know how WAW hazards are prevented though... I am currently reading "ARB: A Hardware Mechanism for Dynamic Reordering of Memory References" to try and find an...
IfThen Software LLC
Today I started reading about memory access. I don't really have much to say on the matter yet, except that it is apparently not as easy to execute multiple memory access instructions at once as it is for integer/float instructions. This mostly stems from the fact that until the instruction is executed, you don't know what memory location it ...
Today I finally finished the section on instruction issuing. This took me a while because I had questions which didn't have readily available answers. Here are the questions I was attempting to find answers to, along with the answers I eventually found (if you have a better answer to any of these questions, please post it in the comments):
If...
If...
Register renaming is the action of replacing the registers used by an instruction with different registers.
When register renaming is used, there are more physical registers (actual hardware registers) than there are logical registers. A logical register is a register which is defined to exist by the architecture, but this is purely an...
When register renaming is used, there are more physical registers (actual hardware registers) than there are logical registers. A logical register is a register which is defined to exist by the architecture, but this is purely an...
Today I finished learning about two of the common (or were common in 1995 at any rate) methods for renaming registers.
First off I should probably explain what "renaming registers" means. In order to have multiple instructions executing in parallel and/or executing out of order (very common nowadays) you need to prevent something...
First off I should probably explain what "renaming registers" means. In order to have multiple instructions executing in parallel and/or executing out of order (very common nowadays) you need to prevent something...
Recent Entries
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DDR SDRAM Memory Bank28 September 2011 -
Memory Access Latency27 September 2011 -
VLIW and Researching Interlocks27 September 2011 -
Instruction Throughput Decides All20 September 2011 -
Scalar But Multiple Functional Units?19 September 2011
Recent Comments
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Data HazardsBy InvisibleMan
Sep 11 2011 07:57 AM -
Data HazardsBy __Homer__
Sep 11 2011 04:17 AM -
De Morgan's LawsBy InvisibleMan
Jun 15 2011 10:06 AM -
De Morgan's LawsBy Mike.Popoloski
Jun 15 2011 09:48 AM -
Well, apparently it's not a prereqBy InvisibleMan
Jun 12 2011 10:22 AM
Recent Entries
-
DDR SDRAM Memory Bank28 September 2011 -
Memory Access Latency27 September 2011 -
VLIW and Researching Interlocks27 September 2011 -
Instruction Throughput Decides All20 September 2011 -
Scalar But Multiple Functional Units?19 September 2011
Recent Comments
-
Data HazardsBy InvisibleMan
Sep 11 2011 07:57 AM -
Data HazardsBy __Homer__
Sep 11 2011 04:17 AM -
De Morgan's LawsBy InvisibleMan
Jun 15 2011 10:06 AM -
De Morgan's LawsBy Mike.Popoloski
Jun 15 2011 09:48 AM -
Well, apparently it's not a prereqBy InvisibleMan
Jun 12 2011 10:22 AM






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