IfThen Software LLC Syndication Sat, 01 Oct 2011 02:39:38 +0000 support@gamedev.net (GameDev.net) IP.Blog 60 http://www.gamedev.net/blog/706/entry-2250702-ddr-sdram-memory-bank/
Data is stored in RAM in an...]]> Thu, 29 Sep 2011 01:31:00 +0000 http://www.gamedev.net/blog/706/entry-2250702-ddr-sdram-memory-bank/ http://www.gamedev.net/blog/706/entry-2250696-memory-access-latency/
if (a > b) c = 6;

Predicated instructions can help to reduce the number of branches in your code, which may increase how...]]> Wed, 28 Sep 2011 01:05:00 +0000 http://www.gamedev.net/blog/706/entry-2250696-memory-access-latency/ http://www.gamedev.net/blog/706/entry-2250695-vliw-and-researching-interlocks/
Today I learned about a couple new techniques. The first one is something called "very long instruction word" (VLIW). In VLIW, a single instruction is actually composed...]]> Tue, 27 Sep 2011 15:03:00 +0000 http://www.gamedev.net/blog/706/entry-2250695-vliw-and-researching-interlocks/ http://www.gamedev.net/blog/706/entry-2250660-instruction-throughput-decides-all/
[b]If a scalar (not superscalar) processor has multiple nonredundant functional units (a single FPU and a single ALU for example) and it issues an...]]> Wed, 21 Sep 2011 04:49:00 +0000 http://www.gamedev.net/blog/706/entry-2250660-instruction-throughput-decides-all/ http://www.gamedev.net/blog/706/entry-2250658-scalar-but-multiple-functional-units/
If a scalar (not superscalar) processor has multiple nonredundant functional units (a single FPU and a single ALU for example) and it issues an instruction to the FPU at a certain clock tick, could it issue another instruction to the ALU at the next clock tick so that...]]> Tue, 20 Sep 2011 03:57:00 +0000 http://www.gamedev.net/blog/706/entry-2250658-scalar-but-multiple-functional-units/ http://www.gamedev.net/blog/706/entry-2250644-researching-thorntons-algorithm/ [list][*]They are both dynamic scheduling methods.[*]They both resolve dependencies (RAW, WAR, and WAW).[*]They are both pipelined.[*]They both have...]]> Sat, 17 Sep 2011 05:39:00 +0000 http://www.gamedev.net/blog/706/entry-2250644-researching-thorntons-algorithm/ http://www.gamedev.net/blog/706/entry-2250637-forwarding-and-out-of-order-scalar-trouble/ Welp, I am still trying to figure out how an out-of-order scalar processor would work. The out-of-order execution part is easy enough, but I am having trouble figuring out how in-order completion would work. To this end, I am currently researching scoreboarding in the hopes of gleaning some hint as to how such a processor would work. If ... Fri, 16 Sep 2011 03:49:00 +0000 http://www.gamedev.net/blog/706/entry-2250637-forwarding-and-out-of-order-scalar-trouble/ http://www.gamedev.net/blog/706/entry-2250634-ooo-execution-with-in-order-completion/
Can a processor have out-of-order execution and in-order completion?
Yes; with one pipeline per active instruction. In other words, for every instruction in the active instruction window (every instruction which can be selected for execution) there needs to be a...]]> Thu, 15 Sep 2011 05:12:00 +0000 http://www.gamedev.net/blog/706/entry-2250634-ooo-execution-with-in-order-completion/ http://www.gamedev.net/blog/706/entry-2250629-reorder-buffer-public-project-tracking/
What is the reorder buffer?
It is a buffer which is used to ensure that instructions commit in-order. It is also used in one method of register renaming. There is one entry for every active instruction. An instruction is active after it has been...]]> Wed, 14 Sep 2011 04:30:00 +0000 http://www.gamedev.net/blog/706/entry-2250629-reorder-buffer-public-project-tracking/ http://www.gamedev.net/blog/706/entry-2250608-execution-scheduling-and-memory-disambiguation/
A processor can be either statically scheduled or dynamically scheduled.

A statically scheduled processor depends on the compiler to create the execution schedule. I am guessing this is either through hints or by actually reordering...]]> Sat, 10 Sep 2011 05:51:00 +0000 http://www.gamedev.net/blog/706/entry-2250608-execution-scheduling-and-memory-disambiguation/