8 replies to this topic

[all_names_taken]

I have a big project that I have been making in visual studio express, in Windows. Now I would like to build it using gcc, in Linux. There are over 200 files, in a folder structure, many of the files are also using external libs etc. Is there any way to effectively create the makefile without manually typing in one entry for each compile target (over 100 entries)?

[arcadestuff]

I've just gone through this myself and I used the autotools suite (automake, autoconf, autoscan etc). This will generate the makefiles and configure script for you. It's a bit of a learning curve (well it was for me anyway) but I think it's well worth it.

The basic gist of it is to create a Makefile.am in each of your source directories which contains a list of source files in that directory and some compiler options, and a configure.ac in the top level directory which contains, amoung other things, a list of the Makefiles. The configure.ac file can be auto generated by the autoscan tool and then you just need to tweak it.

Anyway, if you do a quick google for autotools or automake, autoconf then you should find loads of info. Especially look for info on autoreconf because thats basically a helpfull wrapper around many of the tools that makes things a lot easier.

Here is the first site I found - http://inti.sourceforge.net/tutorial/libinti/autotoolsproject.html

[all_names_taken]

Ok, that's an improvement... but is there nothing even simpler to use available? Such as a GUI based system where I just choose to add a file to project in one dialog (or alternatively, it automatically scans all directories below a given directory for .h, .inl, .hpp, .cpp and .cc files and adds them automatically), and have another dialog where I can add directories and libraries to link to, and then (if needed) a Makefile is generated (or, the appropriate gcc calls are made automatically). In short, something with low learning curve for someone who has used VC Express.

[swiftcoder]

Quote:

Original post by acadestuff I've just gone through this myself and I used the autotools suite (automake, autoconf, autoscan etc). This will generate the makefiles and configure script for you. It's a bit of a learning curve (well it was for me anyway) but I think it's well worth it.

I would recommend CMake (or similar) over the somewhat elderly autotools package. While autotools does get the job done, the learning curve is comparatively quite steep, and cross-platform work can become a nightmare.

Quote:

Original post by all_names_taken Ok, that's an improvement... but is there nothing even simpler to use available? Such as a GUI based system where I just choose to add a file to project in one dialog (or alternatively, it automatically scans all directories below a given directory for .h, .inl, .hpp, .cpp and .cc files and adds them automatically), and have another dialog where I can add directories and libraries to link to, and then (if needed) a Makefile is generated (or, the appropriate gcc calls are made automatically). In short, something with low learning curve for someone who has used VC Express.

It sounds like what you are looking for is an IDE - unfortunately, the majority of IDEs for *nix are not anywhere close to Visual Studio in terms of features or ease of use. You might take a look at Eclipse, which is java based, and sports an optional C/C++ environment.

[hallgeir]

If you are looking for a good cross-platform IDE I'd recommend Code::blocks. :)
It's a great open source IDE for C/C++, you can get it at http://www.codeblocks.org .

Edit: codeblocks also supports using most of the major compilers - GCC, Mingw, the Visual C/C++, +++.

[niteice]

Code::Blocks can also import Visual Studio projects and solutions.

[kRogue]

If you want a simple makefile, but can "grow" to encompass lots of source files, one can do this, it is not pretty, but not so bad, adapt to your file extension for files you are compiling:

Makefile.objList, makefile to list .o files:

#list all .o files to build.
OBJLIST=foo1.o foo2.o

then a makefile for your dependencies:

-include Makefile.objList

#generate dependencies
.depend/%.depend: %.cpp 
	@echo "Making dependency for $<"
	@$(CC) $(CFLAGS) -MM $< > $@

dependencies: $(OBJLIST:%.o=.depend/%.depend)
	@echo "------------------Dependencies made--------------"

and then finally a makefile to actually compile and link:

#choose your compiler
CC=

#and your flags
CFLAGS=

-include Makefile.objList

%.o : %.cpp .depend/%.depend
	$(CC) $(CFLAGS) -c $<


-include $(OBJLIST:%.o=.depend/%.depend) 


Target: $(OBJLIST)
       Yuor link command here.

You can also merge these together.
Mind you there are also ways of saying "complile all .cpp", but I like to explicitly state my .o files.

[Mercure]

There are definitely many ways to compile a project. Here is a very simple yet powerfull enough for many projects. It is based on the following files tree :

project/code/Makefile
project/src/.../*.h
project/src/.../*.cpp
project/test/.../*.h
project/test/.../*.cpp

The code folder only contains the Makefile. You compile your project the first time with:

$ make import
$ make depend
$ make clean
$ make

The second time, you just need :

$ make

If you create or rename files, simply rerun :

$ make import
$ make depend
$ make clean
$ make

The Makefile itself doesn't need to be edited (excepted the variables section at the begining:)

##### Variables

SRCDIR = ../src ../test
INCDIR = -I/usr/include -I../src -I../test
CPPFLAGS = -g -Wall -W $(INCDIR) 
LFLAGS = -lm -lpthread
CC = g++

##### Files

SOURCES = $(wildcard *.cpp)
OBJECTS = $(patsubst %.cpp,%.o,$(wildcard *.cpp))
TARGET = executable

##### Build rules

all: $(OBJECTS)
	$(CC) $(CPPFLAGS) $(OBJECTS) $(LFLAGS) -o $(TARGET)

import:
	@rm -f *.cpp *~
	@for dir in $(SRCDIR); do find $$dir -name \*.cpp -exec ln -s {} \; ; done

depend:
	@makedepend $(INCDIR) -Y -m $(SOURCES) 2> /dev/null

clean:
	@rm -f *.o *.bak *~ *%

##### End of Makefile
# DO NOT DELETE

As you can see, the Makefile way to ease the compilation is to create links for each object files in the code folder.

[all_names_taken]

Ok, thanks! I'll take a look at these different ways soon. As for those with complex makefiles that "generate" dependencies, how can I fit -I and -L flags to gcc into it? Should they be part of the "CPPFLAGS" entry?