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OpenGL and unified address space


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#1 Chris_F   Members   -  Reputation: 1951

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Posted 25 September 2012 - 01:43 PM

Supposedly new and upcoming hardware supports a feature refereed to as "unified address space" whereby the GPU and CPU can share the same address space, which should allow you to transfer data back and forth with nothing but a memory pointer.

I haven't managed to find much practical information on this. How exactly can this be used? Are there OpenGL extensions for this?

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#2 Goran Milovanovic   Members   -  Reputation: 1103

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Posted 25 September 2012 - 02:52 PM

I'm also interested in this.

John Carmack touched on some of that (I think) in this interview: clicky.

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#3 swiftcoder   Senior Moderators   -  Reputation: 9636

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Posted 25 September 2012 - 03:11 PM

Supposedly new and upcoming hardware supports a feature refereed to as "unified address space" whereby the GPU and CPU can share the same address space, which should allow you to transfer data back and forth with nothing but a memory pointer.

As an aside, integrated GPUs have done this for years.

It's especially easy in the integrated case, because the GPU is actually using a portion of main memory as its video memory. This has the odd effect of sometimes making CPU->GPU data transfer much cheaper for integrated GPUs than for faster, dedicated GPUs.

I haven't managed to find much practical information on this. How exactly can this be used? Are there OpenGL extensions for this?

No, and I doubt that there will be, in the near future. Unified address space is much more the domain of OpenCL and CUDA computations - I would expect to see support for unified addressing in both of those.

Edited by swiftcoder, 25 September 2012 - 03:14 PM.

Tristam MacDonald - Software Engineer @Amazon - [swiftcoding]


#4 phantom   Moderators   -  Reputation: 6800

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Posted 25 September 2012 - 04:07 PM

As an aside, integrated GPUs have done this for years.


In fact they haven't; CPUs and GPUs, even integrated ones, use their own address spaces to access the physical memory. What 0x00F4567380 refers to as far as the CPU is concerned is different to what the GPU sees.

AMD's Trinity APUs are, afaik, the first CPU+GPU combo where both parts can access the same memory without requiring a driver to do address translation in any form but it won't be until 2013 that they will be using the same memory controller.

As for the second part of the question; AMD do have some extensions which allow you to 'pin' memory so that it can't be swapped out (GPUs currently can't handle paging in/out of memory so any pages shared must be resident) and thus freely accessed by both CPU and GPU parts - however this is really only useful in the context of an APU otherwise the GPU would be accessing via the PCIe bus which would be a tad on the slow side.

Now, once both the CPU and GPU share the MMU and can respond to page faults accordingly such pinning won't be required, but that's not due until the 2013 time frame from AMD.

#5 swiftcoder   Senior Moderators   -  Reputation: 9636

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Posted 25 September 2012 - 04:16 PM

In fact they haven't; CPUs and GPUs, even integrated ones, use their own address spaces to access the physical memory. What 0x00F4567380 refers to as far as the CPU is concerned is different to what the GPU sees.

That isn't what I meant. Yes, the address space is different, but don't they still have the ability to transfer control of hardware pages back-and-forth?

Tristam MacDonald - Software Engineer @Amazon - [swiftcoding]


#6 phantom   Moderators   -  Reputation: 6800

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Posted 25 September 2012 - 05:16 PM

Until recently I'm 99.999999% sure that isn't the case; on system start up a chunk of memory was reserved for the integrated GPUs and that was all they could see.

If you wanted to copy something to GPU controlled memory then it was copied across from 'system' ram to 'graphics' ram.

That's why AMD's pinning extensions is a pretty big deal as it allows for that zero-copy stuff to work but the GPU doesn't 'own' it, the memory is just locked so it can't be paged out from the physical address; the GPU itself is still just seeing a physical address, all be it one outside of its normal address range.

#7 Hodgman   Moderators   -  Reputation: 27837

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Posted 30 September 2012 - 07:03 AM

Most games consoles use a unified address space from system RAM / GPU RAM (regardless of whether these are physically the same, or separate chips), which sounds pretty cool, but isn't that much of a game changer.
Some random observations:

* Loading of assets is more straightforward. Typically to load a texture, I read it from disk into some malloc'ed memory, then create a GPU texture resource, then copy my malloc'ed memory into the texture resource (map/unmap/update/etc), then free my temporary memory.
On consoles, I can "malloc" some "GPU RAM" directly, and then stream the texture from disk straight into it.

* CPU read-back is still not a good idea, unless CPU/GPU RAM are physically unified as well. Dereferencing a pointer to GPU RAM may be very slow. In my experiences on systems where GPU/CPU RAM are physically seperate, despite being unified in address space, the CPU can write to GPU RAM very quickly, but reads from it ~10 times slower.

* Even if you do want to have to CPU/GPU communicate via shared memory, it's not straightforward. The GPU buffers commands, and is often an entire frame behind the CPU (on PC, it can be even worse, with some drivers buffering up to half a dozen frames of commands at high frame-rates!).
So, say for example that the GPU is producing some data for us, and the CPU wants to consume that data once it's complete -- then as well as having a (unified address space) pointer to the data to read, you also need to use GPU fence/event system, so you can be notified once the GPU has completed that workload.
Or the converse of the above, where the CPU is producing data for the GPU to consume -- if that's some mutable resource, like changing a single pixel in a texture, then you need to insert GPU fences/events so you can tell when the GPU has finished using the previous version of that texture, then perform your modifications after the GPU has passed that fence/completed that event.

To expand on that last one -- on consoles you can work at a level where you've got a lot of synchronisation between the two processors to get the most out of your extremely limited resources (keep in mind the PS3 has a 256MiB GeForce7 and the 360 isn't much better!!).
e.g. we've got 3 objects with procedural textures, but only enough ram for 2 at a time:
You can send off a whole stream of GPU commands in one go, which tells it to draw the 3 objects, but with some important notify/wait points
DrawA using Tex0, Notify DrawA complete, DrawB using Tex1, Infinite Loop C, DrawC using Tex0

You can then prime the CPU so that upon receiving "Notify DrawA complete", it will immediately execute the function that writes out the appropriate texture data for DrawC into Tex0 (which is safe because DrawA is no longer using Tex0).
Meanwhile the GPU continues on with DrawB, and if it completes it before the CPU has done this job, then it goes into an infinite loop (lots of careful hand scheduling work will be done to try and ensure this doesn't happen for efficiency's sake).
When the CPU finishes writing out the new data to Tex0, it overwrites "Infinite Loop C" with "goto next" -- if the GPU hasn't yet reached this command, then when it gets up to it, it will do nothing and move on to the next command (to Draw C using the new Tex0), or, if the GPU has reached the infinite loop, then this will break it out of it so that it can continue to Draw C.

I wouldn't dare try to implement something with such fine-grained CPU/GPU synchronisation via D3D/GL!!

So as you can see, unified address space, plus great event/notification between the two processors, plus explicit knowledge of how CPU->GPU latency and command buffering is implemented, allows you to make the most of both processors... however, this is advanced stuff that's really only done out of desperation on consoles to get by with old hardware. Ideally the above example would be scheduled in such a way that the CPU update job is quicker than the GPU's Draw B job (so that the busy loop isn't executed at all by the GPU), but if your users can upgrade their GPU, then this busy-wait will occur for some users, and they'll get bottlenecked by their CPUs instead.

Edited by Hodgman, 30 September 2012 - 07:10 AM.





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