On a 64 bit CPU registers look something like the following:
64 bits : RAX, RBX RCX RDX (16 of these)
32 bits : EAX EBX ECX EDX (there are 8 of these)
16 bits : AX BX CX DX
8 bits : AH AL BH BL CH CL DH DL
All of the 32 bit registers map in to the corresponding 32 lower bits of the 64 bit registers, and so on downwards until you hit AH and AL which combined form AX .So RAX = 32bits + EAX, so EAX = 16 bits + AX, AX = AH + AL. ( http://www.eecg.toro...es/x86regs.html
The same goes for SIMD registers the AVX/SSE.MMX, so QMM0 = 128bits + XMM0.
Here is a chart
The reason it is useful to know this is when you have to debug a release build, which most of the time means you are staring at Assembly. And in optimised builds clearing only the lower x bit of a previously set register can be achieved by writing to the corresponding register. Also bear in mind that most of the time a optimizing C++ compiler will avoid using FPU instruction as the SIMD ones are faster, even if it has to load between FPU and SIMD registers.