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Question about Program Counter


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#1 warnexus   Prime Members   -  Reputation: 1384

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Posted 11 November 2013 - 09:56 PM

From what I read the Program Counter can hold the address of the current instruction or the next instruction.

 

1) Does that mean it can only hold one of the two at one time? If so, why is this?

 

I also read an instruction needs to get fetched, is the program counter doing the fetching too? I thought it was its job is to hold address of an instruction. blink.png

 

2) When an instruction gets fetched: what does it mean for a program counter to increased its stored value by 1? Is it as easy as adding the number 1 to this value?

 

3) Is the address of the instruction binary or hexadecimal? Is it encoded beforehand before the program counter fetches it?

 

4) If the program counter is holding the address of the next instruction, is the instruction register holding the address of the current instruction?

 

5) Who does the decoding of any of the two addresses of the instructions?

 

I am trying to make sense of both sources I read and it is pretty fuzzy of what is actually happening.

 

 

Source:

 

http://whatis.techtarget.com/definition/program-counter

 

http://stackoverflow.com/questions/15739489/program-counter-and-instruction-register


Edited by warnexus, 11 November 2013 - 09:59 PM.


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#2 King Mir   Members   -  Reputation: 1914

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Posted 11 November 2013 - 10:19 PM

1) Does that mean it can only hold one of the two at one time? If so, why is this?
 
I also read an instruction needs to get fetched, is the program counter doing the fetching too? I thought it was its job is to hold address of an instruction. blink.png

It's 1 register, so it holds one value. When exactly it point to the next or current instruction depends on the architecture. Ostensibly it needs to point to the right instruction when that instruction is fetched, however.
 
2) When an instruction gets fetched: what does it mean for a program counter to increased its stored value by 1? Is it as easy as adding the number 1 to this value?
Yes, assuming that all instructions are the same size for a particular architecture. You can also look at it as increasing the PC by the size of an instruction, where the least significant bits are always 0 and therefore not represented in hardware.
 
3) Is the address of the instruction binary or hexadecimal? Is it encoded beforehand before the program counter fetches it?
There's no difference. binary and hexadecimal are details of how numbers are displayed, not how they are encoded, in this context. Binary can also be considered an encoding, but hexadecimal never is. Binary encoding might be contrasted with Binary coded decimals, but you probably won't need to know that.

4) If the program counter is holding the address of the next instruction, is the instruction register holding the address of the current instruction?
The instruction register would hold the value of the current instruction, like if it's an add or a load or whatever.
 
5) Who does the decoding of any of the two addresses of the instructions?
A block of transistors probably named for their role.
 

Also keep in mind that unless you're looking at a specific microprocessor, these concepts are pretty abstract, and may not exist physically in the same way. But they do model the behavior correctly.

Edited by King Mir, 12 November 2013 - 12:45 PM.


#3 frob   Moderators   -  Reputation: 19006

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Posted 12 November 2013 - 12:25 AM

You are right to be a little fuzzy on what is happening, because what really is happening has gotten fuzzy over the years.

 

Back in the old days -- about 25 years ago -- the CPUs would consume a single instruction and when complete it would modify the pointer.

 

With today's much more complex processors, a CPU can devour multiple instructions at a time. The current x86 family of processors can potentially hold about a hundred decoded instructions at once.

 

Logically it still operates the same way. From the perspective of the disassembler or the perspective of a single CPU instruction the original model is still conceptually correct; an instruction goes in, gets executed, and the pointer is incremented.  It just happens that lots of instructions can be inside the CPU at once, and multiple instructions can be consumed in a single cycle; but they still go in and come out in the right order, so logically it is unchanged.

 

If you want to ignore the details of the CPU internals you can imagine it as the same old black box that was in place three decades ago.


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#4 LorenzoGatti   Crossbones+   -  Reputation: 2542

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Posted 12 November 2013 - 04:20 AM

From what I read the Program Counter can hold the address of the current instruction or the next instruction.

1) Does that mean it can only hold one of the two at one time? If so, why is this?

The program counter and the accompanying notions of current and next instructions are abstractions, very useful to define what the various jump instructions do (choose the next instruction to execute, overriding the default of the one after the current instruction) but not necessarily related to how a processor actually works. Instructions can be executed out of order and simultaneously, making these concepts something that is merely emulated from the point of view of the program.
You can trust a processor to hold the address of an instruction it's fetching for as long as it's needed and then forget it, but there can be a queue of instruction addresses to fetch (possibly shared by multiple hardware threads or multiple cores) or something even more different from a program counter register.

I also read an instruction needs to get fetched, is the program counter doing the fetching too? I thought it was its job is to hold address of an instruction. blink.png

Fetching data from memory is the job of specialized hardware, including the instruction cache. Registers simply hold addresses, which are sent to the appropriate parts of the microprocessor.

2) When an instruction gets fetched: what does it mean for a program counter to increased its stored value by 1? Is it as easy as adding the number 1 to this value?

If you pretend the program is a sequence of instructions, you go to the next one; at the abstraction level of memory addresses you need to account for the length of encoded instructions, which is often variable.

3) Is the address of the instruction binary or hexadecimal? Is it encoded beforehand before the program counter fetches it?

Circuits and registers count in binary (high/low voltage); hexadecimal is only a human-friendly representation of binary numbers that, unlike decimal numbers, doesn't involve carry. But actually it's none of your business, the only addresses you need to read and write correctly are the ones in your program (which can have a far more complex structure with segments, offsets, implicit or discarded bits, etc.).

4) If the program counter is holding the address of the next instruction, is the instruction register holding the address of the current instruction?

The IR is an abstraction (what's the processor doing?) that doesn't correspond directly to microprocessor operation; the instructions being executed are represented implicitly in the configuration of what each register and execution unit do at each clock cycle. Moreover, what's executed is usually a sequence of low-level operations, not the complex instructions in the program.

5) Who does the decoding of any of the two addresses of the instructions?

Usually, dedicated address decoding units (hence the famous historical repurposing of the x86 LEA instruction to do arithmetic); on the cheap, the same ALUs used for general arithmetic (a lot slower). The result is the same, so it doesn't matter for the programmer.
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#5 Álvaro   Crossbones+   -  Reputation: 11962

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Posted 12 November 2013 - 05:26 AM

Just to clarify one thing: IP ("Instruction Pointer") is a synonym for PC ("Program Counter"), commonly used in the x86 architecture.

I think a lot of these issues would become clear if you were to learn the basics of assembly for some architecture. Is that what you are trying to do?

#6 warnexus   Prime Members   -  Reputation: 1384

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Posted 12 November 2013 - 09:31 AM

Just to clarify one thing: IP ("Instruction Pointer") is a synonym for PC ("Program Counter"), commonly used in the x86 architecture.I think a lot of these issues would become clear if you were to learn the basics of assembly for some architecture. Is that what you are trying to do?


I do not mind learning more if it can be make sense of the r type load store and beq diagram. I am struggling to draw all 4 of them free hand in my computer architeture class. I need deep understanding before my mind can help me draw them

#7 King Mir   Members   -  Reputation: 1914

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Posted 12 November 2013 - 12:45 PM

A load gets an address from a register or immediate value, looks it up in memory, and puts the value found in a specified register.

A store gets an address from a register or immediate value and a value to store, and writes it to memory(or the write buffer if that's included in your model.)

Loads and stores can take many clock cycles more than any other instruction because they deal with memory.

BEQ, presumably branch on equal, reads a status register on the ALU, and if it's set appropriately, changes the instruction pointer to point to an offset specified by an immediate value.


It's hard to be more helpful without knowing the specific model your computer architecture course is using. So you should probably ask your professor or people who are familiar with that particular course and can see the assignments you're struggling with.

Just to clarify one thing: IP ("Instruction Pointer") is a synonym for PC ("Program Counter"), commonly used in the x86 architecture.

Yeah that was sloppy of me to use. I changed my above post not to mention IP.

Edited by King Mir, 12 November 2013 - 12:47 PM.





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