Some of the patents listed in the lawsuit lend heavily on previous work, at least to my understanding. Others are so old, relating to hardware T&L and having been filed more than a decade ago, that I can't see them still being applicable to any modern hardware.
Some of them I can't judge. But I aways thought Qualcomm's tiled rendering architecture was significantly different from the early programmable GPUs, and that nVidia's Tegras were the only chips that actually reused that old technology. Does anyone have more insight into this?
Here are the claims and the non-technical descriptions. I copied them from the ITC complaint:
March 6, 2001
"Transform, Lighting and Rasterization System Embodied on a Single Semiconductor Platform"
The ʼ488 Patent discloses a graphics pipeline system for graphics processing, the components of which are positioned on a single semiconductor platform. The operations performed on the single semiconductor platform include transforming graphics data from object space to screen space, performing lighting operations on the data, rendering the data, and executing multiple threads of instructions in parallel on a plurality of logic units while transforming or lighting the data.
January 31, 2006
"Single Semiconductor Graphics Platform System and Method with Skinning, Swizzling and Masking Capabilities,"
The ʼ667 Patent discloses a graphics pipeline system for graphics processing on a single semiconductor platform. The system transforms, lights, and rasterizes graphics data and is adapted to operate in conjunction with a central processing unit. The system is further capable of performing skinning, swizzling, and masking operations involving the graphics data.
May 2, 2006
"Programmable Graphics Processor for Multithreaded Execution of Programs"
The ʼ685 Patent discloses a unified approach for computer graphics sample processing. Various kinds of computer graphics samples, such as vertex samples and pixel samples, are processed in a graphics processor with at least one multithreaded programmable computation unit capable of processing different sample types. The graphics processor includes a thread control unit capable of assigning samples to available threads based on a priority among the sample types. The thread control unit is also capable of dynamically balancing the number of samples assigned to the threads. The graphics processor is also able to process more than one sample type simultaneously.
March 21, 2006
"Method and Apparatus for Multithreaded Processing of Data in a Programmable Graphics Processor"
The ʼ913 Patent discloses an approach for computer graphics sample processing. Various kinds of computer graphics samples, such as vertex samples and pixel samples, are processed in a graphics processor with at least one multi-threaded processing unit. The multi-threaded processing unit is capable of processing samples in an order independent of the order in which the samples were received. For example, instructions in a second thread may be scheduled for execution while instructions in a first thread are stalled waiting for source data.
February 24, 2004
The ʼ063 Patent describes a rendering computer graphics pipeline system that can use screen space tiling (SST) to reduce the memory bandwidth consumed by the rendering system. The computer graphics pipeline system disclosed in the ʼ063 Patent performs SST efficiently, while avoiding the breaking up of primitives. The ‘063 Patent also describes a rendering pipeline design that efficiently renders visible fragments by decoupling the scan/conversion depth buffer processing from certain rasterization and shading processes. A “scan/z engine” resolves visibility and allows the rest of the rendering pipeline to shade only visible fragments.
April 24, 2007
"System, Method and Article of Manufacture for a Programmable Vertex Processing Model with Instruction Set"
The ’140 patent relates to programmable graphics operations in a hardware graphics accelerator. For example, in a system with a central processing unit and a hardware graphics accelerator, the hardware graphics accelerator is used to perform programmable operations on graphics data. The programmable operations are performed utilizing instructions from a predetermined instruction set.
February 10, 2004
"System, Method and Article of Manufacturer for Shadow Mapping"
The ’372 patent relates to graphics operations of a programmable shader in a graphics pipeline. In particular, shading calculation may be performed through a shader program, including successive operations on a fragment’s color or texture-related operations in which the output of the first shading calculation is saved for use by the second shading calculation and where the calculations include decoupled variables.