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Fathom Update

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Azh321

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I am about to make the third revision to my virtual cpu, Fathom. This last one should support just about everything that I plan to add to it and there shouldnt be any more major changes after its complete.

But there are some design decisions I have come to, specifically about the instruction set. The Z80, IIRC, uses up to 4 or 5 bytes for certain instructions. But I orginally wanted Fathoms instruction set to use only a single byte per instruction, though thats impossible if it has a 16bit address bus. Now, I could squeeze most of the instructions (such as all of the variations of the LD instruction) into a single byte, if I cut down on the number of registers and such. But I didnt like that idea, nor did I like the idea of having to do something like
LD R0, 5
LD R13, R0
Instead of being able to do:
LD R13, 5

So I guess what im going to do is only have the core instruction in the first byte. What I mean by that is, LD RX, RX will have its own instruction and be expecting the next byte to specify which two registers it is acting on. I could also go somewhere in the middle of these two choices, some instructions fit all of the variations in the first byte, while others expect a byte after it.

Does anyone get what im saying? Or even care? :)
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The extra long instructions on the Z80 are usually down to using a prefix byte, eg $DD makes the following instruction uses IX instead of HL. In the interests of code density I'd probably use a similar scheme whereby you have small, fast, specific instructions where possible and longer generic instructions where not.

Sounds like an interesting project, and I look forwards to reading more about it!

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