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DMA is Good

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Caitlin

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I am currently putting the finishing touches on the DMA control portion of the GPC. I have decided to use superior yet harder to find Intel DMA chips rather than the Zilog types. Why? Because they are much better to interface hardware to. Here is the schematic of the DMA section:



This circuit takes eight DMA request lines from expansion slots plus two from the main board, prioritizes them, and presents them to the CPU in accordance with system timing specifications. Automatic address control and bank switching for 16 banks of 64kb of memory is also provided.

Here is the timer section, which is pretty simple:



This section includes six individual counter/timers on two Intel 8253 CTC chips. One counter/timer from each chip is connected to multiplexing/demultiplexing circuitry to allow the selection of 1 count/timer input from an array of 8 inputs. Both of these timer/counter circuits can be chained together or looped through software control. Again (see my reply concerning PIN5 and /EO), pins are left floating in the schematic for now because there is circuitry which belongs to the CTC block but is routed through the interrupt block for proper function.

As is my custom in designing circuits, this can be slightly modified to work with most older Intel based designs (which includes the Z80). If you are familiar with older Intel hardware you will notice that the circuit uses Intel control signals. These signals are routed through the "system control" protion of the main board in order to interface directly with the CPU being used.

The expansion ports of this system pose several problems which I will enjoy solving. The most significant is the ability to move data between expansion ports without involving the CPU or system busses. So the CPU could be doing calculations such as figuring out how to traverse an obsticle, while data is being streamed from an video sensor/converter card to a vision processor card (this is just an example), all without interfering with each other. Currently I'm thinking about using a microcontroller to control the expansion busses. This is a good idea because it allows adaptive streaming of data between ports unlike DMA.
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You know, you scare me sometimes :P

I was suddenly reminded of when I was undergrad and had that computer architecture course. I had to hand wire a 4 bit ALU on a bread board, in only 3 hours :/

That was back when I had long nails. You get work done a lot faster with nails than tweezers.

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Oh don't get me started on the ALU, and yes, you are right, long nails help breadboarding A LOT. It sucks though because if your nails are done they get messed up, so you can figure that I don't do much breadboarding when my nails are done :p Now that you have mentioned it, I don't do much breadboarding anymore.

I scare you? Good, very...good...mwhaa, mwhaa....

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I don't particularly like using my fingers when breadboarding, what you need to do is invest in a super pair of pliers that let you grab, poke, and prod to your heart's content :)

It seems you've left a lot of pins floating - that can't be good can it?

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I remember all those pracs as well, when I tended to solder my own fingers together. At least with software enginnering all you have to worry about is RSI, rather than burning your fingers [smile]

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All the pins except those labeled "PIN5" and "/EO" have connections to other parts of the main board. The problem is that I'm still debating on what functional block of the board the circuits they are connected to belong. The circuits ARE directly related to DMA, but won't function properly without first going through the system control block.

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Wow. Looking at this makes me want to go back to college to study EE and CE. Then again I should go back and finish my CS degree. Details details.

Hope you go on to create some very intresting systems. :)

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I suppose I didn't look at it close enough, it looked like there were a bunch of floaters. :) I just turned in a huge circuits project today so any circuit looks awful right now.

This is wayyy out of my field of expertise, but isn't the DMA supposed to assert /EOP when the transfer is complete? Or is that what you're saying and I'm just too out of it to see it? Or perhaps I'm just plain wrong? :)

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Yes, EOP is asserted by external (from the view of the DMA controller) devices when the transfer process is complete. That part of the circuitry references signals from system control (and expansion control). This is my dilemma, it IS part of DMA but requires external signals to operate. Maybe I'll just throw it in the DMA section and be done with it.

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LOL, I wish you luck. I hate timers, I just got finished messing with synchronization for hours on end for a class project.

It's just, dealing with both edge-sensitive and level-sensitive clocked devices, add in gated clocks, and asynchronous memory devices, and trying to make the whole mess work together and it's enough to make you want to say all right little chips, let's see how you like a 4GHZ clock, take that!

*ahem* back to normal

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