This circuit takes eight DMA request lines from expansion slots plus two from the main board, prioritizes them, and presents them to the CPU in accordance with system timing specifications. Automatic address control and bank switching for 16 banks of 64kb of memory is also provided.
Here is the timer section, which is pretty simple:
This section includes six individual counter/timers on two Intel 8253 CTC chips. One counter/timer from each chip is connected to multiplexing/demultiplexing circuitry to allow the selection of 1 count/timer input from an array of 8 inputs. Both of these timer/counter circuits can be chained together or looped through software control. Again (see my reply concerning PIN5 and /EO), pins are left floating in the schematic for now because there is circuitry which belongs to the CTC block but is routed through the interrupt block for proper function.
As is my custom in designing circuits, this can be slightly modified to work with most older Intel based designs (which includes the Z80). If you are familiar with older Intel hardware you will notice that the circuit uses Intel control signals. These signals are routed through the "system control" protion of the main board in order to interface directly with the CPU being used.
The expansion ports of this system pose several problems which I will enjoy solving. The most significant is the ability to move data between expansion ports without involving the CPU or system busses. So the CPU could be doing calculations such as figuring out how to traverse an obsticle, while data is being streamed from an video sensor/converter card to a vision processor card (this is just an example), all without interfering with each other. Currently I'm thinking about using a microcontroller to control the expansion busses. This is a good idea because it allows adaptive streaming of data between ports unlike DMA.