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# CRC

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I posted something like this about a week ago, but I never got any replies and the post died away Hopefully I can get some better feedback! Anyway, I have a few issues with CRC. First, it claims to be a straight Modulo-2 divsion of the polynomial into the data stream. However, unless I''m mistaken, this isn''t the case in practice. When we are performing a CRC, we first need to start with an initial value in the register - it can actually be completely random, but must be consistant. Wait a second. If we''re supposed to be dividing the data stream by the polynomial, why do we need some potentially random, predetermined initial value? In the case of a 16-bit CRC, shouldn''t we load the actual first 2 bytes of the data stream into the register? What''s going on? Second, when it''s time to shift, we left shift the register, and left shift the data stream, BUT we don''t left shift the data stream INTO the register. Is there some XOR trickery going on behind my back where the LSB of the register ends up with the correct value? Or is it another one of those quirky things? So what''s up with this CRC? It''s performed like a Modulo-2 division, but not with the real data. Is this intentional?

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Since this is your second post that dies on the subject, I think I''m not the only one who is totally clueless about CRC. Could you provide a short explanation/hyperlink? I made a short search, but a lot of things are named CRC, apparently.

Cédric

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I dont know about CRC, but i searched google for ''CRC polynomial'' (no quotes) and it came up with quite a few sites on CRC algorithms. try looking there.

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Believe me, I've spent days reading all the pages They explain the technical details pretty well, but I haven't found one that explains the discreptency between an actual Modulo-2 division between the data and the polynomial, and this "fake" one, which resembles a division in a lot of ways but appears to have a few holes, such as initial values and data/register independent shifts.

These are the three best links I have:

http://www.4d.com/ACIDOC/CMU/CMU79909.HTM
http://utopia.knoware.nl/users/eprebel/Communication/CRC/

They explain the subject best.

[edited by - Zipster on August 20, 2002 11:27:41 PM]

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To be honest, I don''t know how CRC works, I just snarfed that code and held faith.

quote:

why do we need some potentially random, predetermined initial value?

This one however, I know, because you have the same problem with check-sums. A zero-length stream (null-data, i.e. bug/fubar receive) will generate a checksum/CRC of 0. The extracted value from the non-existent data will likely either be intialized to zero, or spuriously zero. Then when you compare the sent CS/CRC to calculated CS/CRC it will pass the test - on completely bogus (non-existent) data.

Hence, you want to use a non-zero seed if possible. So using the first word/dword of the data it not a good idea, since it''ll also be zero in the aforementioned communication failure mode.

And if you''re iteratively processing data, a zero-length update could very well be a valid case, and should not cause a fault.

quote:

Second, when it''s time to shift, we left shift the register, and left shift the data stream, BUT we don''t left shift the data stream INTO the register. Is there some XOR trickery going on behind my back where the LSB of the register ends up with the correct value? Or is it another one of those quirky things?

Almost have to post the code, shifts with carry come to mind, or perhaps they are shifting indexes?

1. 1
2. 2
3. 3
Rutin
22
4. 4
JoeJ
16
5. 5

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