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Krylloan

BTS asm instruction.

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Krylloan    142
I was just looking through the a page on the intel x86 instruction set. http://www.penguin.cz/~literakl/intel/intel.html I saw the command "BTS". Am I right in thinking I could use this as a very quick mutex? basically, the mutex functions are just
inline int openMutex(int *mutexValue) {
    byte rtn;
    __asm {
        BTS *mutexValue, 0
        SETC rtn
    }
    return rtn;
}

inline void closeMutex(int *mutexValue) {
    *mutexValue = 0;
}
will this work? will this work on a multi-cpu system?

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walkingcarcass    116
BTS is bit-test-set.
BTS EAX, 3
will copy the third (well, fourth) bit of EAX into the carry flag and then set it in the register

BTC clears the bit in the source after copying it to carry

BT just copies the bit

so these two pairs of instructions are functually the same

BT CL, 0
jc some_label

AND CL, 1
jnz some_label

********


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Krylloan    142
I understood what bts does from the (edit) page.

The reason I thought this would be useful for a mutex is that it avoids the situation:

1) Thread a: calls openMutex().
2) Thread a: tests mutex value to see if it's available, and gets a true result.
3) Op Systm: swaps between thread a and b.
4) Thread b: calls openMutex().
5) Thread b: tests mutex value to see if it's available, and gets a true result.
6) Thread b: sets mutex bit to unavailable.
7) Thread b: executes code inside mutex.
Op Systm: swaps back to thread a.
8) Thread a: sets mutex bit to unavailable.
9) Thread a: executes code inside mutex "simultaneously" with thread b.

Because nothing can occur between stages 2 and 8, since this is only a single instruction.
I assume cache-coherency protocols will ensure that other processors cannot begin a BTS before another BTS is ended on the same piece of data.

I was just wondering if anyone with more experience in ASM could tell me if I am right.

[edited by - Krylloan on August 7, 2003 11:37:45 AM]

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walkingcarcass    116
it all you''re testing for is zero/nonzero it would be more efficient to use test followed by setc or cmov

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Krylloan    142
Um walkingcarcass, the idea is to prevent anything happening between the test and the set.

The OS could decide to change threads after "TEST" but before "CMOV". This would mean the original thread has entered the mutex without preventing other threads doing so. BTS prevents this.

Also, my link doesn''t seem to have CMOV. Is this a new instruction or is this site just not complete? Do you have a better x86 ISA link?

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Sneftel    1788
Yes, IIRC, BTS is specifically meant for mutexes.


How appropriate. You fight like a cow.

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Guest Anonymous Poster   
Guest Anonymous Poster
walkingcarcass:
The BTC (bit test & complement)instruction doesm''t necessarily clear a bit; it complements a bit. Now, the BTR (bit test & reset)instruction clears a bits

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stevie56    145
The BTS instruction will do as you require.

On exit you will have the original state in the carry flag, and the bit is set on.

Can''t say anything about a multiprocessor system, though. If all processors directly access that part of memory, then they should ''see'' the same thing. If they only see a ''shadow'' of that part of memory, then one processor changing it won''t tell the others unless they are instructed to update their shadows.

Hope this helps.

Stevie

Don''t follow me, I''m lost.

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