I was just looking through the a page on the intel x86 instruction set. http://www.penguin.cz/~literakl/intel/intel.html I saw the command "BTS". Am I right in thinking I could use this as a very quick mutex? basically, the mutex functions are just

inline int openMutex(int *mutexValue) {
    byte rtn;
    __asm {
        BTS *mutexValue, 0
        SETC rtn
    }
    return rtn;
}

inline void closeMutex(int *mutexValue) {
    *mutexValue = 0;
}

will this work? will this work on a multi-cpu system?

I understood what bts does from the (edit) page.

The reason I thought this would be useful for a mutex is that it avoids the situation:

1) Thread a: calls openMutex().
2) Thread a: tests mutex value to see if it's available, and gets a true result.
3) Op Systm: swaps between thread a and b.
4) Thread b: calls openMutex().
5) Thread b: tests mutex value to see if it's available, and gets a true result.
6) Thread b: sets mutex bit to unavailable.
7) Thread b: executes code inside mutex.
Op Systm: swaps back to thread a.
8) Thread a: sets mutex bit to unavailable.
9) Thread a: executes code inside mutex "simultaneously" with thread b.

Because nothing can occur between stages 2 and 8, since this is only a single instruction.
I assume cache-coherency protocols will ensure that other processors cannot begin a BTS before another BTS is ended on the same piece of data.

I was just wondering if anyone with more experience in ASM could tell me if I am right.

[edited by - Krylloan on August 7, 2003 11:37:45 AM]

Um walkingcarcass, the idea is to prevent anything happening between the test and the set.

The OS could decide to change threads after "TEST" but before "CMOV". This would mean the original thread has entered the mutex without preventing other threads doing so. BTS prevents this.

Also, my link doesn''t seem to have CMOV. Is this a new instruction or is this site just not complete? Do you have a better x86 ISA link?

Yes, IIRC, BTS is specifically meant for mutexes.

How appropriate. You fight like a cow.

walkingcarcass:
The BTC (bit test & complement)instruction doesm''t necessarily clear a bit; it complements a bit. Now, the BTR (bit test & reset)instruction clears a bits