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makefile dependency syntax

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I have 2 vars holding lists of files in a makefile. and I want it so that each elt in LIST_OUTPUT is dependent only upon its corresponding element in LIST_INPUT. I can''t use subst b/c the two lists vary quite a bit, I''d simply like to be able to check on the position or element number of $@ in LIST_OUTPUT and then scroll down to that number in LIST_INPUT
LIST_INPUT := $(IN_DIR)/a.txt $(IN_DIR)/b.txt $(IN_DIR/c.txt
LIST_OUTPUT := $(OUT_DIR)/a_Global.txt $(OUT_DIR)/b_Global.txt $(OUT_DIR)/c_Global.txt

# rest of makefile

   @$(ECHO) This doesn''t work b/c it checks dependency against all elements in LIST_INPUT

$(LIST_OUTPUT): $(LIST_INPUT[$(position $@,$(LIST_OUTPUT))])
  @$(ECHO) This doesn''t work b/c well, I made up that syntax and the function called ''position''

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Makefiles can be quite a pain in the ass if you want to do something clever. I solved a similar problem in a way that might not be useful to you but i will show it anyway... it does require GNU make though, since i use some extended functionality. With ''standard'' make you really can not do anything fancy i''m afraid.

I used ''blocks'' of variables like this:
TARGETS = 1 2 3

TARGET1 = vfsc.exe
SOURCE1 = vfsc.cpp logfile.cpp bitmap.cpp
LIBS1 = opengl32

TARGET2 = generate.exe
SOURCE2 = generate.cpp logfile.cpp genlib.cpp

TARGET3 = something.exe

then you can use $(foreach ID, $(TARGETS), $(TARGET$(ID))) to get a list of the TARGETX vars. It is awful, but it works and it is the best i could come up with given the limited stuff make can do.


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