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Making GNU make only compile what it needs to

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I just started using GNU make and g++ a short time ago. I''ve noticed that make recompiles code that hasn''t been changed since the last time I compiled it. How do I make it only recompile changed code?

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it has something with the structure os Makefile
it is composed of targets, each target may depend on other target or file
here is some example:

all: bin

CC=g++

bin: one.o two.o
$(CC) -o bin one.o two.o
one.o: one.c one.h my.h
$(CC) -c -o one.o one.c
two.o: two.c two.h my.h
$(CC) -c -o two.o two.c

It has one main target bin, which is combination of two source files one.c and two.c
one.c includes one.h and my.h
two.c includes two.h and my.h

[edited by - glubo on February 8, 2004 3:26:48 PM]

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