Does IEEE specify an 80 bit float format?
The x86 architecture does all floating point internally at 80 bits, so I was wondering, is this an IEEE (754 or not) specified format that it works with, or is it entirely x86 specific? And can someone post the actual format?
No. Intel's 80-bit format is just used internally by the CPU to minimize error that accumulates durring operations ... especially multiplication/division. The final results are still placed in a 32-bit/64-bit register. There is no way of directly accessing these 80-bit wide registers the CPU uses.
I'm not sure, but I *think* the format is a 1-bit sign, 63-bit mantissa, and 24-bit exponent.
How wrong I was.
[Edited by - Aprosenf on October 7, 2004 8:35:21 AM]
How wrong I was.
[Edited by - Aprosenf on October 7, 2004 8:35:21 AM]
> There is no way of directly accessing these 80-bit wide registers the CPU uses.
The FPU does indeed provide versions of FLD and FSTP that access 80 bits.
> I'm not sure, but I *think* the format is a 1-bit sign, 63-bit mantissa, and 24-bit exponent.
bbut that adds up to 88 :) It is 1, 15 and 64 bits. When accessing such values in memory, they are split into 16 bit exponent and 64 bit mantissa (the bus is 'only' 64 bits wide). Aside from that convenience, width=64 allows lossless 64-bit integer arithmetic on the FPU.
The FPU does indeed provide versions of FLD and FSTP that access 80 bits.
> I'm not sure, but I *think* the format is a 1-bit sign, 63-bit mantissa, and 24-bit exponent.
bbut that adds up to 88 :) It is 1, 15 and 64 bits. When accessing such values in memory, they are split into 16 bit exponent and 64 bit mantissa (the bus is 'only' 64 bits wide). Aside from that convenience, width=64 allows lossless 64-bit integer arithmetic on the FPU.
Right Jan, found this at Intel :
http://developer.intel.com/technology/itj/q41999/articles/art_6.htm
Double-extended precision M=15, N=64
IA-32 double-extended precision M=15, N=64
Full register file double-extended precision M=17, N=64
@Promit :
Why do you need this format specs ?
I remember using it for packed rgb bilinear filtering before the MMX. I would only care of that in asm code, where you can ensure that intermediates are kept 80 bits precise in the register stack instead of being r/w in memory.
http://developer.intel.com/technology/itj/q41999/articles/art_6.htm
Double-extended precision M=15, N=64
IA-32 double-extended precision M=15, N=64
Full register file double-extended precision M=17, N=64
@Promit :
Why do you need this format specs ?
I remember using it for packed rgb bilinear filtering before the MMX. I would only care of that in asm code, where you can ensure that intermediates are kept 80 bits precise in the register stack instead of being r/w in memory.
I was just curious. I've been studying the MIPS architecture and IA-32/x86 is an interesting contrast to look at.
Thanks for the link Charles, very interesting stuff :) Didn't know that 80 bit long doubles are indeed codified by IEEE, nor of the existence of a 82 bit internal format.
Hehe, when compared against other architectures, IA always looks so bad ;)
Quote:I was just curious. I've been studying the MIPS architecture and IA-32/x86 is an interesting contrast to look at.
Hehe, when compared against other architectures, IA always looks so bad ;)
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