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freka586

Stencil/Z/alpha culling

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I have a few questions on stencil (etc.) culling. My application runs some *very* computationally expensive code on say 30% of the pixel in an image. This seems to be an ideal situation for dynamic branching. Unfortunately I have not been able to get DB to work on my 6800GT. To still be able to cull the other 70% of the pixel I currently use a stencil culling approach. A first shader pass sets alpha values that are kept or culled, before doing the expensive pass. My problem now is that I *need* full access to the depth/stencil buffer. I need to be able to (manually) both read and write depth values. So, first off - is there a way to lock depth buffers with stencil capability? I have not found a format that allows both. If not, maybe I need to do my culling in a different way? I am not sure in what pipeline order Z/stencil/alpha cull is done - could I get the speedup of today with some other culling technique? Or should I perhaps ditch the culling all together, since dynamic branching "should work", maybe it is only a matter of drivers/APIs?

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After doing some thinking I guess depth culling sounds like it might be an option.
So, when in the pipeline is depth culling performed - would I still get the current speedup?

Would this work, given "the right" render state and setting correct depth in pass 1?

Pass 1) Check if pixel should be rendered. Set depth to (cull) or (keep).
Pass 2) Render full pass (including depth) for kept pixels

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Since I write depth in the pixel shader this invalidates early Z on FX line of hardware.
(This requires that interpolated depth values are used, and DEPTH writes invalidates the feature.)
Is this also the case for the 6800 class of hardware?

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On geforce 6 series cards, writing Z in the shader will eliminate early z culling when writing z, but if you turn off writing z later, subsequent primitives will get early z culling from z values you wrote explicitly in the z buffer.

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