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FalShen

make questions

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Yo, noob here. Or actually, not noob. Just a noob with make. Very nice, that thing, it's just: I can't get it work with different directories. I once worked with Ant, very nice, but Ant makes problems with the 'sdl-config' script. I wanna put all my sources into one directory ([...]/src), then the objects ([...]/obj) and the executable in the root dir of the project... I can't get it to work, make makes problems I can solve, and the documentation has huge holes on that topic. Or maybe I'm just too stupid, who knows... Anyway, I hope you can help me, and forgive my stupitidy... Scánkalantesh...

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Does this makefile work for you?


test.exe: obj\test.o
gcc -o test.exe obj\test.o

obj\test.o: src\test.c
gcc -o obj\test.o src\test.c -c



Place it in the root directory of your project, which contains subdirs src\ and obj\. This will compile a source file src\test.c, placing the object file in obj\ (obj\test.o), and the executable file in the root directory.

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Sorry, but not really...
I tried that, yeh, but I wanna but them all into one variable... I tried this:

OBJECTS = main.o game.o
SRCDIR = src
OBJDIR = obj

colin: $(OBJECTS)
$(CC) $(CFLAGS) -o $(OBJDIR)/$(OBJECTS)

%.o: %.cpp
$(CC) $(CFLAGS) -c -o $(OBJDIR)/$@ $(SRCDIR)/$<


but somehow... I dunno, it doesn't work out

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Quote:
Original post by FalShen

%.o: %.cpp
$(CC) $(CFLAGS) -c -o $(OBJDIR)/$@ $(SRCDIR)/$<


but somehow... I dunno, it doesn't work out


Does the base version work?


%.o: %.cpp
$(CC) $(CFLAGS) -c -o $@ $<;

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You might want to do what most projects do:
1. Create a general-purpose makefile that compiles all sources in current directory.
2. Copy such makefile to each directory.
3. Recursively call makefiles in child directories.
4. Each recursive call will also move compiled .o files to target location (just like VC++ does).

For 1. - refer to the thread I linked.

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Quote:
Original post by FalShen
Well... that could be the problem... It is looking for the file in the root directory, isn't it? How can I solve that?


me thinks: copy the makefile to each directory and call that recursively.

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well, it works now with this code:

CC = g++
CFLAGS = -O3 -s `sdl-config --cflags`
LFLAGS = -O3 -s `sdl-config --libs`
OBJECTS = main.o
EXECUTABLE = colin
SRCDIR = src
OBJDIR = obj

all: $(EXECUTABLE)

$(EXECUTABLE): $(OBJECTS)
$(CC) $(LFLAGS) -o $@ $(OBJDIR)/$(OBJECTS)

%.o: $(SRCDIR)/%.cpp
$(CC) $(CFLAGS) -c -o $(OBJDIR)/$@ $<

Well... I'd also like to see the solution with the recursive calls... But it's solved.
Thanks to everyone!

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Quote:
Original post by FalShen
How do I make recursive make calls?


all:
make -C some_directory_1
make -C some_directory_2
mv some_directory_1/*.o $(BUILD_DIR)
mv some_directory_2/*.o $(BUILD_DIR)


How to automagically get list of directories to maintain such a command-list, I do not know at the moment. I got to think a bit...

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Quote:
Original post by FalShen

$(EXECUTABLE): $(OBJECTS)
$(CC) $(LFLAGS) -o $@ $(OBJDIR)/$(OBJECTS)

%.o: $(SRCDIR)/%.cpp
$(CC) $(CFLAGS) -c -o $(OBJDIR)/$@ $<



It seems to me like it will be recompiling the whole project each time, since the
%.o: $(SRCDIR)/%.cpp
directive wil be searching for local .o files, when they will be already in $(OBJDIR).

Quite crappy, IMO.

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Just for reference:


$dir1 = dir1/
$dir2 = dir2/
$files1 = f1.o f2.o f3.o
$files2 = f4.o f5.o f6.o

all: addprefix($dir1,$files1) addprefix($dir2,$files2)


Works fine for smaller projects.

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