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Hey guys, I have just started to learn VHDL and I am really confused how it works. This is NOT my hw. This is a part from lecture notes and I just want to understand what all this means. I've put a quote in front of lines I need clarification on. Also I using "ModelSim XE III". How can I simulate the waves for this code? Thanks a lot!
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY TestExample1_vhd IS                   -- What does this part DO???
END TestExample1_vhd;

ARCHITECTURE behavior OF TestExample1_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT example1
PORT(
R : IN std_logic;
S : IN std_logic;
Q : OUT std_logic;
Qbar : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL R :  std_logic := '0';
SIGNAL S :  std_logic := '0';

--Outputs
SIGNAL Q :  std_logic;
SIGNAL Qbar :  std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: example1 PORT MAP(                    -- ALL OF THIS???
R =&gt; R,
S =&gt; S,
Q =&gt; Q,
Qbar =&gt; Qbar
);

S &lt;= '1' after 20 ns, '0' after 25 ns, '1' after 60 ns, '0' after 65 ns;
R &lt;= '1' after 40 ns, '0' after 45 ns, '1' after 60 ns, '0' after 65 ns;
END;


[Edited by - musafir2007 on October 29, 2007 3:27:08 AM]

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I'm not sure I remember this correct, but I give it a shot.

ENTITY declares the input and output ports for the component being declared. In this case, TestExample1_vhd does not have any input or output signals.

PORT MAP is used to create components and connect signals to its inputs and outputs. You create a component called uut of type example1, and connect the signal R to uut.R, S to uut.S, and so on. That is, R and S are connected to uut's input, and Q and Qbar are conneted to uut's outputs.

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Thanks Bob! but a little bit more detailed clarification will be appreciated...
thanks!

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Every component have input and/or output signals, and ENTITY and PORT MAP is all about declaring what input and output signals a particular component have, and how signals are connected with the components.

Your test example doesn't have any input or output signals, but the example1 component does. The port map command explains how the internal signals are connected to the uut object.

This is all very fundamental parts of VHDL, and if you're struggling with this, I suggest you talk to the teacher about it instead of over a forum, becuase VHDL is a lot about component port mapping. Online forums is great for small and quick details, but not for major concepts.

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