What are ROPs & TMUs?

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13 comments, last by IrYoKu1 14 years, 5 months ago
Texture Addressing:
http://msdn.microsoft.com/en-us/library/ee422486(VS.85).aspx

The point is that a filterung unit is only able to compute one bilinear sample per cycle. If you are using trilinear or AF the filtering units are looping a few times to generate the sample and the TAUs are idling. So the IHVs started to use less TAUs than TFUs because most texture samples are not only bilinear anymore. With TAU/TFU = 0.5 you get trilinear or 2x bilinear AF for free (1 TAU cycle). 2x trilinear AF still needs 2 TAU cycles.

But the TAUs are getting cheaper compared to the TFUs (new compression modes etc) and the shaders nowadays are using a lot of data that should not be filtered. So the last generations are using again a TAU/TFU = 1.0.
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Quote:Original post by CV
The point is that a filterung unit is only able to compute one bilinear sample per cycle. If you are using trilinear or AF the filtering units are looping a few times to generate the sample and the TAUs are idling. So the IHVs started to use less TAUs than TFUs because most texture samples are not only bilinear anymore. With TAU/TFU = 0.5 you get trilinear or 2x bilinear AF for free (1 TAU cycle). 2x trilinear AF still needs 2 TAU cycles.

But the TAUs are getting cheaper compared to the TFUs (new compression modes etc) and the shaders nowadays are using a lot of data that should not be filtered. So the last generations are using again a TAU/TFU = 1.0.


How you learned this stuff? Can you recommend me a book/url to learn this low-level GPU architecture/organization details? The closest thing I found is a chapter in GPU Gems 2 that talks about the architecture of the GeForce 6X generation.

Thanks!
Quote:Original post by IrYoKu1
How you learned this stuff? Can you recommend me a book/url to learn this low-level GPU architecture/organization details? The closest thing I found is a chapter in GPU Gems 2 that talks about the architecture of the GeForce 6X generation.
Thanks!


There's no "here's our secrets" book simply because there's a lot of NDA and trade secrets there. You know the picture, but you don't exactly know the internals of each video card unless you work at NVIDIA or ATI.

With that said, you can always read the tips each HW vendor makes, which tells you a lot of how they work (sometimes you just figure out with a little trial & error and putting the pieces together).
Also reading old stuff helps a lot. "TMUs" were very new in fixed function DX7 hardware, where it was cutting edge being able to blend two or three textures in a single pass because the "card has multiple texturing units". There used to be a lot of specific HW designed for each task, but they had a problem: they weren't programmable, not flexible.
Now with shaders everything's integrated and borders between different HW components are less blurry. Even shaders limits are blurry. Once we talked about "pixel shader units" & "vertex shader units" but today gpus come with "unified shaders" which are able to perform both stuff.

Useful links which can explain how hardware works (even if it doesn't directly talk about HW):
NVIDIA GPU
Programming Guide

Depth in
depth

How MSAA works
ATI explaining how dynamic flow control works in their GPU cards.

Oh, and you may have noticed, visiting NVIDIA's and ATI's developer sites and reading all their papers helps, a lot.

Cheers
Dark Sylinc
Quote:Original post by IrYoKu1How you learned this stuff?

To be honest... I don't know.
I was always interested in new architectures (cpu/gpu) and tried to understand the design decisions. Mostly it's just a hobby. (having access to all console sdk's might help a bit sometimes ;) )

Newer architectures are a lot more complicated, so it's a good idea to start with older ones.

Here are some more resources:
anandtech.com (e.g. http://www.anandtech.com/video/showdoc.aspx?i=2870)
ixbtlabs.com
chip-architect.org (old cpu architectures)
Beyond3d forum
3DCenter forum (if you understand german)
CUDA SDK documentation
AMD STREAM SDK documentation
Conference Papers/Presentations
hardware design lectures at university



Thanks!

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