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sheep19

A question about pagetables and paging

5 posts in this topic

Hi,

First, I didn't know in which forum to post. If this is not a good one, please move it to another.

I recently learned about how pages are layed out in memory.

There is something I don't understand though.


--
Let's say that I have a 16 bit system, where pages are 32 bytes long and it uses a [b]two level paging system[/b].
So, I have 16 bits for address, from which 5 are used as the offset (to select each bytes from the 32 in a page).

Now, 11 bits remain. How do I select which to use for what?
How many bits should I use for the root page table? (5 or 6)
How many bits should I use for the user-space page table?
It would seem that 5 for each would be ok, but what about the extra bit?

Thank you.
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Which kind of pages?

In one part of your post it sounds like you mean a page:offset model.

In another part it sounds like you are meaning virtual memory pages.

A little more context, please?
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It sounds like he means standard virtual memory. You generally want to use all your bits (a minor preference would be 6 on pages, since some hardware has optimization or functional requirements that only work within a single directory), in order to maximize your virtual address space (well, at least until your address space is so huge you can save some resources by disallowing the high ranges). Keeping the 2 levels new equal minimizes the average and worst case page walk time, however, the actual optimal decision really requires more info about the caching schemes used, in particular, the TLB implementation.
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I'm sorry for not providing more information.

I'm asking about page tables (mapping a process' virtual
pages to physical pages in RAM)


[quote]
You generally want to use all your bits (a minor preference would be 6 on pages, since some hardware has optimization or functional requirements that only work within a single directory), in order to maximize your virtual address space (well, at least until your address space is so huge you can save some resources by disallowing the high ranges). Keeping the 2 levels new equal minimizes the average and worst case page walk time, however, the actual optimal decision really requires more info about the caching schemes used, in particular, the TLB implementation.
[/quote]

Pages are 32 bytes (2^5). So it means that 5 from the 16 bits of a virtual address are needed to offset into a page.
11 bits remain. [b]Can I split them anyway I want?[/b] (even if that's not good in terms of efficiency)

For example:
3 bits for level-0 index, 8 for level-1 index, 5 offset
5 bits for level-0 index, 6 for level-1 index, 5 offset
etc

Thank you for your time.
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Functionally, you can split it any way you like, but generally you want to minimize your page walk iterations on TLB misses (usually requires a 50/50 split), and make sure that all the other system specific constraints are optimized for.
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