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Cairn

How are virtual addresses translated?

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[color=#000000][font=Arial,]I understand that (for intel) the virtual address translation process is :[/font][/color]

[color=#000000][font=Arial,][b]1.[/b] The incoming virtual address is divided into a page table number, a page number, and an offset.[/font][/color]

[color=#000000][font=Arial,][b]2.[/b] The process desriptor base register (PDBR) in the CPU tells where the directory starts.[/font][/color]

[color=#000000][font=Arial,][b]3.[/b] The page table number is multiplied by four to use as an offset into the directory, and the directory entry is looked up.[/font][/color]

[color=#000000][font=Arial,][b]4.[/b] The directory entry contains the address of the page table, and validity and protection information. If this information says that either the page table isn't present in memory or the protections aren't OK, the translation stops and an exception is raised.[/font][/color]

[color=#000000][font=Arial,][b]5.[/b] The page number is multiplied by four to use as an offset into the page table, and the page table entry is looked up.[/font][/color]

[color=#000000][font=Arial,][b]6.[/b] The page table entry contains the address of the page, and validity and protection information. If this information says that either the page isn't present in memory or the protections aren't OK, the translation stops and an exception is raised.[/font][/color]

[color=#000000][font=Arial,][b]7.[/b] The offset is used as an index into the page.[/font][/color]

[color=#000000][font=Arial,][b]8.[/b] The data is at the address finally arrived at.[/font][/color]

[color=#000000][font=Arial,]And that all makes sense up to step [b]6[/b] which is where I get confused because the table entry format only specifies [b]20 bits[/b] for the physical page frame address which means the physical page address has to be in a [b]1 megabyte [/b]range, or are the 20 bits shifted left 12 bits, (multiplied by 4096: size of page) giving it the ability to address [b]4 gigabytes?[/b][/font][/color]
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The phsyical addressess stored in the page table (depending on flags you have set this may be at one or two levels of indirection for PAE) are the upper 20 bits of the address. Hence why pages are typically 4k in size (hint, the remaining 12 bits make up 0-4095.
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When you say remaining 12 bits you mean from the original virtual address right?
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What I read said that the upper 20 bits [b]are [/b]the address when it should be read as the the upper 20 bits [b]of[/b] the address
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Simplest answer: Your pointer in user-land is really a handle and the page table translates it to a real address behind the scenes.\

The 'obsolete' segment registers and the upper 20 bits are used to figure out what real page has the memory, and the lower 12 bits are addressed into that to find the bits.
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