[color=#000000][font=Arial,]I understand that (for intel) the virtual address translation process is :[/font]

[color=#000000][font=Arial,]1. The incoming virtual address is divided into a page table number, a page number, and an offset.[/font]

[color=#000000][font=Arial,]2. The process desriptor base register (PDBR) in the CPU tells where the directory starts.[/font]

[color=#000000][font=Arial,]3. The page table number is multiplied by four to use as an offset into the directory, and the directory entry is looked up.[/font]

[color=#000000][font=Arial,]4. The directory entry contains the address of the page table, and validity and protection information. If this information says that either the page table isn't present in memory or the protections aren't OK, the translation stops and an exception is raised.[/font]

[color=#000000][font=Arial,]5. The page number is multiplied by four to use as an offset into the page table, and the page table entry is looked up.[/font]

[color=#000000][font=Arial,]6. The page table entry contains the address of the page, and validity and protection information. If this information says that either the page isn't present in memory or the protections aren't OK, the translation stops and an exception is raised.[/font]

[color=#000000][font=Arial,]7. The offset is used as an index into the page.[/font]

[color=#000000][font=Arial,]8. The data is at the address finally arrived at.[/font]

[color=#000000][font=Arial,]And that all makes sense up to step 6 which is where I get confused because the table entry format only specifies 20 bits for the physical page frame address which means the physical page address has to be in a 1 megabyte range, or are the 20 bits shifted left 12 bits, (multiplied by 4096: size of page) giving it the ability to address 4 gigabytes?[/font]

When you say remaining 12 bits you mean from the original virtual address right?

What I read said that the upper 20 bits are the address when it should be read as the the upper 20 bits of the address