Dunno if there's assembly people here, but I figured I'd ask a couple questions and see what happens. Here goes...

1) Looking at the documentation in the "Intel 80386 Reference Programmer's Manual" I see that for some instructions (ie "xor m32,imm32") there's no +m documented on the cycle count. Is the instruction sent to the bus to be executed remotely?

2) While studying stack behavior in the VS debugger I compiled the following:


int func(int arg, int artoo) {
int a = 0xAAAAAAAA;
int b = 0xBBBBBBBB;
int c = 0xCCCCCCCC;
int d = 0xDDDDDDDD;
//breakpoint
return 12;
}


at the break I expected ESP to point to the sequence:

"DDDDDDDD CCCCCCCC BBBBBBBB AAAAAAAA"

but instead I got:

"CCCCCCCC DDDDDDDD BBBBBBBB AAAAAAAA"

is there some kind of reason for re-arranging the variable order? I mean it's not erroneous, since the vars are referenced at the correct addresses, but why re-arrange them?

Thanks to anyone that takes the time to respond.

It just struck me as strange that something like that would be done. I mean I can see how if there's no standard then the compiler would likely just compose and dump the list as quickly as possible, ignoring order, but seeing how the stack arrangement is already moderately complex I guess I'm just surprised that there's no standard. It means that I can't look at the var declaration order in the C(++) and infer the correct stack positions in inline asm (Although that would be a pretty arcane thing to need, since I can just refer to the actual variable name, I guess.), so I was wondering if it was something that was done deliberately in order to gain some form of run-time benefit.

Thanks for your reply.

Any clue about question 1 though? That's the one that's really been puzzling me. I was optimizing a tight inner-loop the other day and I was counting cycles to compare between the compiler code and the optimized code (optimized code - 9 cycles per loop; compiler code 80+2m cycles per innerloop, lol - that was a damn good optimization - saves about 20 sec per execution on my 2.41 ghz cpu) and I noticed that operations that write to memory don't have +m cycles, but just a flat cycle count. Does the system bus do some of the work here or something? I'm just wondering if this is an error in the documentation or if the CPU actually does not need to fetch the memory value in order to apply a modification to it.

Did you compile that with full optimizations and release build?

Nah, that one was with everything turned off. It clipped the vars in opt modes because they're not referenced.

As for your other question, I don't know. Independent instructions are usually executed in parallel with memory fetches, if that's what you mean.

What I mean is uh... Let's see...

...

Actually, now that I'm looking at it again there's some stuff here that doesn't make sense. Like 'JMP rel16' is 7+m, which it shouldn't be since JMP rel just changes the value of EIP (unless this is assuming the wait time for fetching the instructions at the new EIP address). I guess I'm misunderstanding the convention the book is using. I assumed that +m meant that a bus wait was included in the execution time.

I've only had the actual instruction reference pages until now. I just downloaded the full text last night, so I'll read through the rest and see if I can figure out what's going on.

Thanks again for replying.