I Wish Intel CPU's Had A Linear Interpolate Instruction
Software isn't good enough?
Why linear only, why not all the other interpolation functions?
Why linear only, why not all the other interpolation functions?
A linear interpolate operation is just (max - min)*p + min which can be computed with 2 instructions using a fused-multiply add. That is max - min is one instruction and then the multiply and add is another. This is planned for future processors.
That said there are more important instructions we need in the future like those predicate instructions to remove branch pipeline flushes.
That said there are more important instructions we need in the future like those predicate instructions to remove branch pipeline flushes.
Agreed. Linear interpolation is not even a blip on the performance radar.
Branch misprediction is a big one. Frequent operations like matrix multiply are another big one.
Branch misprediction is a big one. Frequent operations like matrix multiply are another big one.
Agreed. Linear interpolation is not even a blip on the performance radar.
Branch misprediction is a big one. Frequent operations like matrix multiply are another big one.
DPPS in SSE4 handles the matrix multiplication case perfectly fine. You're not likely to ever see a single matrix multiply instruction on the x64 platform. MADD is about as good as it'll get (i.e. DPPS)
The branch misprediction one is perhaps the largest one I can thank of that stands out as far as performance critical code goes.
Does x86 support branch-hints? I've gotten some modest gains on PPC from adding likely/unlikely hints to branches inside tight loops, but then again, PPC's branch predictor is a lot more primitive than your typical x86 one...
While we're at it, does x86 have [font=courier new,courier,monospace]fsel[/font] (or conditional-move for all register types)?
While we're at it, does x86 have [font=courier new,courier,monospace]fsel[/font] (or conditional-move for all register types)?
There are prefix bytes for branch taken and branch-not-taken hints for Jcc instructions (3E and 2E respectively). No idea how to use them in assembly language, though (I mainly work on disassembly, not assembly, and I just ignore the hint prefixes since I'm not attempting to round-trip). I've never actually seen them in the wild though.
x86 has quite a lot of conditional-move opcodes, but I don't remember if all register types are supported or not. I believe that GPR and FPU registers are supported, but not sure about MMX/XMM/YMM.
x86 has quite a lot of conditional-move opcodes, but I don't remember if all register types are supported or not. I believe that GPR and FPU registers are supported, but not sure about MMX/XMM/YMM.
Didn't SSE2 introduce a couple branch hint opcodes?
[...] Additionally, Branch Hints were introduced. These hint prefixes are used to help the processor perform better branch prediction.
hwnt - Hint Weakly Not Taken.
hst - Hint Strongly Taken.[/quote]
@http://softpixel.com...g/simd/sse2.php
This topic is closed to new replies.
Advertisement
Popular Topics
Advertisement
