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KaiRohmer

Shader Branching Costs for "constant" Conditions

6 posts in this topic

Hey,

im wondering if there is a specified behavior for branches in shader code if the condition is not really dynamic.

While searching the forum i found some hints that dynamic branching is not possible if some functions like Sample(...) are used. What if the condition is a value defined in the constant buffer? In this case all threads are following the same path and evaluating both paths is theoretically not requiered. Is this depending on the compiler and driver or are there any specified  and documented rules?

 

with shader i mean sharder in general rendering pipeline and compute shader or cuda.

 

Thanks

- Kai

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I actually played with it 2 days ago, tried a bunch of shaders on GTS650 and Intel's HSW integrated GPU. It seems that there is some cost to uniform-dynamic-branching. I tried several workloads and got somewhere between 1%-4% performance improvment when removing those branches.

 

I can think of a 2 reasons:

1. Even though it's uniform, it's still a branch, and that limits the HLSL and driver compilers in optimizing code around that branch. I have verified it looking at the generated HLSL code.

2. AFAIK, there's no branch predictor in GPUs, and the GPU stalls until the branch is resolved. Sounds resonable, but I'm not sure if that's actually true.

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If the compiler can tell that it's constant data (you're probably not that lucky with some value somewhere in constant memory, but you never know), there may be no branch at all. In that case, the cost would obviously be zero. But you cannot rely on that.

The single biggest, devastating effect of branching is when different threads in a warp take different paths ("diverged warp"). In the worst case, this causes a 1/warp_size slowdown (so if you have warps of, say, 64, that's quite painful). In addition, this may further stall when there are several dynamic branches, since there is usually only a single reconvergence stack per warp, so it isn't possible on the hardware side to enter a second dynamic branch before the slowest thread from the previous one has reconverged.
This is why e.g. nVidia recommends to run at least 6 warps per multiprocessor in their "Optimizing Cuda" presentations, because this asserts that the GPU has always enough left over warps to dynamically swap threads in and out as they are stalled (on read-after-write register dependencies, or branches).

For constant data, diverged branches obviously aren't a problem, all threads necessarily take the same branch. The data is likely read from cache on pretty much every architecture, too, after the first warp has run (on Kepler, constant memory is dedicated read-only cache memory, so it will "hit" on the first warp as well), so the memory access will be fast. There's no branch prediction on any GPU to my knowledge, but without any concrete number being named, non-diverged branches allegedly only take "a few cycles". In my experience, "a few" means "about 20".

20 cycles sounds like an awful lot, but note that GPUs are ... weird beasts, compared to CPUs. Harmless instructions such as multiplication or instruction sequences (like integer add followed by a dependent integer add) may have latencies around 25-30 cycles due to register dependencies (see e.g. http://www.ece.lsu.edu/gp/notes/set-nv-org.pdf for implementation details on nVidia). GPUs are built to deal with this by swapping threads in and out.

 

So, in one word, I wouldn't worry. If the condition is constant, you're probably good.

Edited by samoth
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If the compiler can tell that it's constant data (you're probably not that lucky with some value somewhere in constant memory, but you never know), there may be no branch at all. In that case, the cost would obviously be zero. But you cannot rely on that.

The compiler can't remove a branch is it has a dependency on a CB value, only if it constant during compilation.

 

 

 


non-diverged branches allegedly only take "a few cycles". In my experience, "a few" means "about 20".

My 3-lights-shader is 330 SM5.0 instructions long. If I add a branch to check if each light is enabled, I get to 350 instructions. 6% more instructions for a single branch. If you have other branches (like specEnabled, shadowEnabled, diffuseEnabled) - this number will be even higher. GPUs will hide some, but not all, of this latency. SIMT architectures (NV) will probably do better than SIMD.

[EDIT] GPUs will actually not hide latency due to the extra instructions. For the GPU, nothing that require thread change happened, there are just more instructions to execute.

 

But - I do agree that the performance impact is usually to small to care about. I'm just a performance lunatic...

Edited by satanir
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The data in a constant buffer is not really constant... it is dynamic. The only truly constant data that I know of are the values declared with "static" (in HLSL), and the constant numeric literals that are used inline or in a #define etc... At the highest optimization level, the compiler should not even generate the data allocation for the "static" variables (register storage), if all you do is use them in a branch condition, and it will not even generate a branch in the resulting assembly, if it already knows what the condition evaluates to, which is the case when the condition consists of only "static" constant elements. In this case, the part of the branch that evaluates to "true" will always be added to the final shader binary, while the  "false" branch will not be added.

Edited by tonemgub
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The compiler can't remove a branch is it has a dependency on a CB value, only if it constant during compilation.

 

 

The data in a constant buffer is not really constant... it is dynamic

 

Well yes, that is why I said "You will probably not be that lucky". Technically, constant memory is just normal memory of which you promise not to touch it, and on some architectures, it exists as dedicated L1 cache (in addition to the normal L1 cache, but it isn't being updated, ever). Insofar, all the compiler can tell is that you access "some memory" (which may be "some special memory", but still, some memory whose contents aren't known at that time).

 

In principle, however, the compiler can tell that it's constant at compile time, since you use the __constant__ keyword (in e.g. CUDA), and a clever compiler could in principle know that the data can never ever possibly change after you memcopied data using its API. There is no way your shader can modify the data, and there is no way you can access this data, except by the driver's public API, which the driver will immediately know about the moment you do. Thus, the compiler might secretly, on the fly, generate a special version of the shader based on what data you upload. In theory, that is. And, this may equally be a win or a loss, depending on how intrusive the recompilation is.

 

nVidia OpenGL drivers have been known to do that kind of thing in the past (I believe some 5-6 years ago), which has lent to big surprises for example when there was  suddenly a small "hiccup" after setting an uniform to exactly 2.0 or 0.0 -- after which the frame rate "magically" went up. For some time, it was therefore recommended to use values like 2.00001 to avoid this "surprise". I'm not sure if drivers still do that kind of thing today, but it's conceivable.

 

Depending on how fast the compiler can generate an alternative binary (this is presumably much faster than parsing the whole thing and starting from scratch), you might not even notice that this happens between the time when you set the buffer and when you launch the kernel.

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On any decently-modern hardware (within the past 4 or 5 years) it should have a very low overhead. These GPU's no longer have a high overhead from using branch instructions, and branching on a value from a constant buffer ensures that it will be 100% coherent between neighboring threads so you don't have to worry about divergence.

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Thanks for this nice discussion!

I just wondered what would happen if have two branches with heavy usage of the texture units. E.g, Different shadow tests for standard shadow maps and hemispherical shadow maps.

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MJP is basically right. However, if one side of the branch is much more complicated than the other, you can still end up with a non-obvious performance penalty, due to register pressure decreasing occupancy. Basically, the compiler needs to allocate enough registers to do all of the work in either side of the branch. If you have a rarely taken branch that triggers very complex code (ie code that requires lots of registers)... then the shader will always reserve that many. That means that you can get fewer copies of your shader running. If the workload is fairly balanced (between different code paths), then this doesn't really matter.

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