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abdellah

where are the 4 addresses of an integer

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if we conseder this line :

int n = 5;

 

how i get the 04 addresses of the integer n?

 

2/ question 2 : can an integer be stored in 04 separated addresses?

 

thank's

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What language? Probably C or C++, but I don't like being a mind reader. I believe you are trying to ask how to get the memory address of each memory element (call it a byte) in an integer, assuming that integer uses 4 bytes to compose that integer. I say "assuming" because, although it is common for int to have a size of 4, it isn't guaranteed to be. Since this sounds like homework I'm afraid I'm not going to directly answer your question. Instead, I will point out that you should consider the address-of operator operator, '&'. Once you know the address of a variable, do you know how to get the following address of that int? It would be 4 bytes following, right? What if you had 'char n' , got the address, and then got the following address? It would be 1 byte following, right? Is there a way you can get the address of an int and treat it like you got the address of a char?

 

Hopefully by understanding the answer to the first question the answer to the second will be easier to comprehend and answer.

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This appears to be very much a homework question (a basic programming course question at that).

 

As such I recommend you read up on the address of operator (&) and the various C++ cast operators (especially reinterpret_cast). Do note that integers are not guaranteed to be 4 bytes in size (noted previously), and that casting around a pointer of one type to another can be implementation or undefined behavior.

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it is question of my mind, do you want (any of you) want how the Professor & the Doctor RON PETROCHA (Worker in Microsoft (i think .NET team)) answer me?

 

secondly, i have understand from (nobodynews) is that if the address is like 0x01 so the rest 3 address are (the 3 bytes) are 0x2 , 0x3 & 0x4

Edited by abdellah

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There are systems where bytes are not 8 bits. There are systems based around 36 bits, 18 bits, 15 bits, and 9 bits, and other combinations.

Might I ask what systems these are besides embedded DSP's, and if you know why the design choice for a non power of 2 word (or sum of two power of 2's) addressability was chosen?  You have my curiosity. 

 

edit - oh and in the case of 36,18, and 9 bits I assume you're not talking about parity or ECC bits.

Edited by Infinisearch

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and if you know why the design choice for a non power of 2 word (or sum of two power of 2's) addressability was chosen?  You have my curiosity.  oh and in the case of 36,18, and 9 bits I assume you're not talking about parity bits.

Nope, not parity bits.  
 
Addresses and addressability are a fun thing in computers.  
 
For a very long-lived business and scientific product, OS2200 is still alive and kicking. Most were/are based on 36-bit words, but they had methods to address in 18-bit, 9-bit, and 6-bit ways. Most of the old PDP machines, DEC supercomputers, and Univac machines were this size. This type of machine was used by tons of businesses, schools, governments, military simulations, and scientific groups, were 18-bit architectures. IBM and Unisys still make and support these systems for large organizations.
 
In my university days one of the labs had a PDP8, which was 12 bit words. We also had a PDP-11, which was 16-bit.  During an assembly course in the 2nd year we were required to write tiny programs in assembly for several machines, not just x86.  The class focused on x86 assembly, but we were exposed to R10000 chips (the SGI boxes), M68000 chips (apple desktops, but the chip was used for many popular calculators and game consoles), and PDP machines (which were used by many businesses and military simulations).
 
IBM's System/38 and AS/400 derived systems are 48-bits for addresses. Those include the whole iServer rebranding they have been doing in recent years. They're used by an enormous number of scientific and business sever racks. These systems are still quite popular in established institutions, especially banks.  If you were a big business and you bought a bunch of POWER8-based computers for your business since they are just coming out this month, you'll find the instruction set uses 48-bit pointers. Today they don't use special 48-bit memory registers, they just put them into 64-bit registers, but the address portion is still 48-bit. If you have any friends in the corporate computing world, you can have fun and interesting discussions about how those play out.
 
 
 
And maybe a surprise for you: the box you are likely using right now, a modern x86 processor, may be using any of 36-bit, 40-bit, 48-bit, or 52-bit addressing, with 48-bit being the currently common choice over the last 8 years. Obviously none of these are a power of two. 
 
That all happens with the magic of virtual memory and paging tables. CPUs started using paging tables all the way back in 1995, where the Pentium Pro started using 36 bit values so the OS and CPU could manage hardware with more than 4GB of physical memory. AMD took a different direction, offering 52-bits for controlling values, and later 40 bits. There was a bit of a fight between AMD and intel over control of the instruction set between 2001-2004, and the consensus ended up being the current 64-bit extensions in x86-64. The first few rounds of the 64-bit extensions exposed 40 bits, later rounds moved to 48 bits. The virtual memory is managed by the OS and CPU with page tables, that encode both the address range and the page table in addition to the location within the page tables. The OS presents it to 32-bit applications in 32-bit blocks and to 64-bit applications as 64-bit blocks, but when the OS is working with the CPU for virtual memory paging and process management, virtualized memory operates with 48-bit addresses.  With 64 bit extensions enabled in X86-64, the hardware still operates at 48-bit addresses and encodes them to unique 64-bit address spaces. 
 
So today x86-64 CPUs currently only operate at 48 bits since no individual devices today even approach that much actual memory space. (IBM's Watson supercomputer had 16 terabytes of ram, but it was spread across almost 3000 machines and was on a different architecture) Thanks to the way it is encoded in the future the hardware can grow to support multiple exabytes of ram (beyond 2^64) on the hardware and still provide the same 64-bit virtual environment if needed. Virtualization is fun that way.
 
This isn't the first time the x86 family used non power of two. Before the 32 bit era the x86 family used to use 20 bit addressing with a segment:offset format. You had a 16-bit segment, and it was added to another 16 bit offset. At the time, that was an enormous number, one whole megabyte, when 'big' computers had memory measured in tens of kilobytes. You may not be old enough, but Google for the quote "640K ought to be enough for anybody." The format meant things could be addressed in lots of different ways. Assuming I do my math right, it meant 00FF:0000 is the same as 00EF:0100, which is the same as 00EE:0110, which is the same as 0088:07700. All were addresses to the same spot in memory. So even though they used two 16-bit values to reference it, x86 used 20 bit addresses.

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For a very long-lived business and scientific product, OS2200 is still alive and kicking.

Thanks for this, mandated by the government huh, its interesting for me.  I was aware of all the x86 stuff, and the gist of the x64 stuff and addressing in general but thanks for taking the time.  Out of curiosity was the 15bit word size a DSP or something else?

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