Jump to content
  • Advertisement
Sign in to follow this  
Mr_Fox

DX12 uav barrier and atomic operation

This topic is 590 days old which is more than the 365 day threshold we allow for new replies. Please post a new topic.

If you intended to correct an error in the post then please contact us.

Recommended Posts

Hey Guys,

 

Think about the following case:

You have multiple dispatch calls with compute shader which launches tons of threads, and each thread will do an atomic add on the same memory location (same address for all threads from all dispatch calls). Since DX12 allow dispatch to be overlapped, all related document will suggest to put a uav barrier between each dispatch since they all operate on same buffer, and has data dependency.

 

I can understand the reasoning for normal read/write, since you read/write will be cached in multiple level, and to get correct result, you need to flush your cache, and do bunch of related cache invalidation. So that's why we need uav barrier between dispatches.(is my understanding correct?)

 

But what if all my write is atomic as described in the above case? In my experience, atomic write will be immediate visible to all other threads from the same dispatch even if threads are in different execution unit (I am not super sure about that, since no doc specifically state that....), which, to me, means all cached data is synced across entire GPU. And if that is the case, I think it will be safe to remove uav barrier between dispatches since data cache has already been taken care, there is no out-of-date data.

 

And from my experiment, it seems to work correctly on my GTX680m without the barrier. But there is no official document out there can confirm it, so I have no idea whether it is officially safe to do it, or it will cause undefined behavior, or corrupted data, and I am just accidentally get the correct result.

 

Please correct me if my assumption is wrong, and it will be great if someone could explain how atomic operation works in GPU (especially for those support reading back the original data, since it seems atomic read/write bypass all caches)

 

Thanks in advance

Share this post


Link to post
Share on other sites
Advertisement

I don't think UAV barriers flush any caches, they just ensure an execution order (I could be wrong, but IIRC UAV's are implemented on the standard cache hierarchy which is coherent).  Which leads to point two which is if the order of execution does not matter then don't use UAV barriers.

 

edit - oh and IIRC atomics are implemented in the L2 cache which is shared by different execution units.

Edited by Infinisearch

Share this post


Link to post
Share on other sites

oh and IIRC atomics are implemented in the L2 cache which is shared by different execution units.
 

Thanks Infinisearch, so does that mean all atomic read/write(on uav) bypass L1 cache (which is only shared within EU?), and which gives all read/write behavior kinda equivalent to the std::memory_order_seq_cst

Share this post


Link to post
Share on other sites
edit - oh and IIRC atomics are implemented in the L2 cache which is shared by different execution units.

BTW I only know this about AMD's GCN architecture

 

 

 

Thanks Infinisearch, so does that mean all atomic read/write(on uav) bypass L1 cache (which is only shared within EU?), and which gives all read/write behavior kinda equivalent to the std::memory_order_seq_cst

 

I don't know if it bypass's it but it acts as a cache miss (since the L1 and L2 are coherent and inclusive).  I'm not really familiar with std::memory_order_seq_cst so I can't really comment on it but I will say how do you guarantee execution order within a wave/warp?  I don't think you can so if what you're doing has an order to it, it won't work.  Only coarse grained order using barriers is possible.

 

edit - nevermind that last part.

Edited by Infinisearch

Share this post


Link to post
Share on other sites

This might clear things up for you.

From this page: https://msdn.microsoft.com/en-us/library/windows/desktop/dn903898(v=vs.85).aspx

 

  • D3D12_RESOURCE_UAV_BARRIER - Unordered access view barriers indicate all UAV accesses (read or writes) to a particular resource must complete before any future UAV accesses (read or write) can begin. The specified resource may be NULL. It is not necessary to insert a UAV barrier between two draw or dispatch calls which only read a UAV. Additionally, it is not necessary to insert a UAV barrier between two draw or dispatch calls which write to the same UAV if the application knows that it is safe to execute the UAV accesses in any order. The resource can be NULL (indicating that any UAV access could require the barrier).

Share this post


Link to post
Share on other sites

Thanks Infinisearch, I should have read the doc more carefully, but it's good to know that in my case it is safe to remove the uav barrier B-)

Share this post


Link to post
Share on other sites

You're welcome... but did you read into that quote?  If I'm not mistaken it implies there's no flushing of the cache necessary for writes to become visible to subsequent dispatches.

Share this post


Link to post
Share on other sites

 If I'm not mistaken it implies there's no flushing of the cache necessary for writes to become visible to subsequent dispatches.

 

yup, I have that kept in mind. My read will be in a much later pass, and I transit it into a srv for just reading, but before that, all dispatch just do atomic access(though these including atomic read like interlockedadd, but it should be safe according to some answers in my other post), so should be fine.

Share this post


Link to post
Share on other sites
Sign in to follow this  

  • Advertisement
×

Important Information

By using GameDev.net, you agree to our community Guidelines, Terms of Use, and Privacy Policy.

We are the game development community.

Whether you are an indie, hobbyist, AAA developer, or just trying to learn, GameDev.net is the place for you to learn, share, and connect with the games industry. Learn more About Us or sign up!

Sign me up!