On NVidia, yes they do have big bank on "constant" registers that they will pre-load with cbuffer data at the start of a draw.
On AMD, cbuffers are just like any other buffer... However, they will act differently because each lane (e.g. pixel) is reading the same addresses.
AMD does have some constant registers... But only 16 of them (of 32bit size, so 64bytes total) per draw so they're usually used to store cbuffer descriptors/etc rather than actual constants though. This is all exposed to the user in D3D12, so you get to choose how to use those 64bytes!
AMD shader cores are basically just SIMD64 CPU cores that compute 64 pixels at a time. They have a bunch of 32bit register used when doing work that is uniform across all lanes (e.g. load a constant) and a bunch of 32bit_simd64 registers used for lane-varying (per pixel) work, and there's instructions that operate on each type of register.
Say you write a pixel shader like:
int y = ... // Some per pixel value
float x = mySrv[y];
And one like:
float x = myConstant;
These would compile into psuedo asm like:
int32_simd64 y = ... // Some per pixel value
SRV mySrv = gather_uniform(cb0, 0);// fetch SRV0's descriptor from a driver-generated cbuffer for use by all lanes.
float32_simd64 x = gather32x64(mySrv, y);//load 64 floats from that SRV
and:
float32 x = gather_uniform(cb1, 4); // load one float from cb1 at offset 4 bytes.
As above, once one core does one of these loads, the data will be present in the L2$ and subsequent cores will be able to load that same data very quickly.