Hello

I've been wondering for some time, when compiling a HLSL shader, and inspecting the assembly code, the vector - matrix multiplications can either result in four dp4 or four mad instructions depending on which side I am multiplying from.

My question is, is there a difference in performance, should I worry about it? At the moment, all of my shaders in my engine are using dp4 instruction for that (because I started it from some tutorial that used it that way...). I know that on the final hardware specific code after CreateXSShader, that is not documented, but are there any guidelines to follow?

Thanks, as I thought, so it doesn't matter any more.

I remember back in the old days, that we were encouraged (by the hardware vendors) to choose the dp4 version, as the order of the instructions doesn't change the outcome. Back then the compiler(s) had a tendency to shuffle the instructions around, and the order of the madd instructions could result in numerical different results which again could result in z fighting when using a multipass approach.

I don't know how good (or bad) the compiler is nowadays in maintaining the order, as I'm still using the dp4 approach ;-)

Around what generation of GPU's did it stop mattering?

NVidia's first SIMT architecture (as opposed to the older SIMD/vector style) was the Geforce 8 series (if I remember correctly).

By SIMT you basically mean unified shaders right? Going by what you linked that still appears to be a vector architecture. I looked at the linked (from your link) sucessor fermi and that appears to be scalar.

NVidia's first SIMT architecture (as opposed to the older SIMD/vector style) was the Geforce 8 series (if I remember correctly).

By SIMT you basically mean unified shaders right? Going by what you linked that still appears to be a vector architecture. I looked at the linked (from your link) sucessor fermi and that appears to be scalar.

Nah unified shaders means they no longer have separate hardware for vertex shading vs pixel shading. The GeForce 7 had this split, so you could have pixel-shading cores sitting idle while the vertex-shading cores were maxed out... :(
GeForce7 pixel shaders used SIMD instructions (like SSE) - so each pixel could operate on a float4 per clock. GeForce 8 (Tesla) ran 8 pixels per "core" using scalar instructions (float) and Fermi bumped up to 32 pixels per "core", still using scalar instructions per pixel.