I am researching the Nintendo Game Boy's hardware and due to my non-existent electrical engineering background I am unable to understand some of the technical terms and events that are occurring at the circuitry level.
Upon powering on the Game Boy, execution starts at $0000 with the internal ROM which contains the boot program. When a value (appears to be $1) is written to address $FF50 the internal ROM is disabled and $0000 - $0100 of the cartridge ROM is mapped back to that address space.
The above image shows the hardware layout of the CPU, address bus, data bus, address decoder, memory selector circuit, internal ROM, external ROM, and internal RAM. It was my understanding prior to reading https://www.google.com/patents/US5134391 that when you wrote $1 to $FF50 it changed state of some piece of hardware which controlled mapping the address space. My understanding was partially correct. From reading the patent documentation I discovered that the MSC sent out a chip select signal, CS1 and CS2, that somehow enabled/disabled the internal ROM and external ROM respectively. The confusion lies within the fact that when the CS1 signal is sent out it appears that only the internal ROM is enabled, and therefore external ROM is non-accessible and and vice versa when the CS2 signal is sent. That is fine and dandy, however I don't understand how that signal enables and disables the ROM's. Also when CS2 is sent out and the external ROM is enabled, only addresses $0100 - $7FFF are mapped. How are the interrupt vectors and what not between $0000 and $0100 accessed if the memory isn't mapped? It appears that there is no state that allows the whole $0000 - $7FFF of the external ROM to be accessed. When CS1 is set you only can access the internal ROM and when CS2 is set you can only access a portion of the external ROM.
I hope that maybe somebody could clear this up for me as I am completely lost at the moment.
Thank you,
BagelBytes