I am researching the Nintendo Game Boy's hardware and due to my non-existent electrical engineering background I am unable to understand some of the technical terms and events that are occurring at the circuitry level.

Upon powering on the Game Boy, execution starts at $0000 with the internal ROM which contains the boot program. When a value (appears to be $1) is written to address $FF50 the internal ROM is disabled and $0000 - $0100 of the cartridge ROM is mapped back to that address space.

The above image shows the hardware layout of the CPU, address bus, data bus, address decoder, memory selector circuit, internal ROM, external ROM, and internal RAM. It was my understanding prior to reading https://www.google.com/patents/US5134391 that when you wrote $1 to $FF50 it changed state of some piece of hardware which controlled mapping the address space. My understanding was partially correct. From reading the patent documentation I discovered that the MSC sent out a chip select signal, CS1 and CS2, that somehow enabled/disabled the internal ROM and external ROM respectively. The confusion lies within the fact that when the CS1 signal is sent out it appears that only the internal ROM is enabled, and therefore external ROM is non-accessible and and vice versa when the CS2 signal is sent. That is fine and dandy, however I don't understand how that signal enables and disables the ROM's. Also when CS2 is sent out and the external ROM is enabled, only addresses $0100 - $7FFF are mapped. How are the interrupt vectors and what not between $0000 and $0100 accessed if the memory isn't mapped? It appears that there is no state that allows the whole $0000 - $7FFF of the external ROM to be accessed. When CS1 is set you only can access the internal ROM and when CS2 is set you can only access a portion of the external ROM.

I hope that maybe somebody could clear this up for me as I am completely lost at the moment.

Thank you,

BagelBytes

According to the CPU manual, section 2.6. Cartridge Types, the cartridge is mapped to 0000 onwards, not 0100. The cartridge contains the interrupt vector table.

Yes, the cartridge ROM is mapped to $0000 - $7FFF. However according to the following documentation, when CS2 is set, only $0100 - $7FFF is mapped:

In the case where the first and second character data become coincident with each other and the complement data are also coincident in the comparison processes in the step S15 and S17, the CPU core 24 in step S19 outputs the write signal WR. In response, as previously described with reference to FIG. 6 and FIG. 7, the RS flip-flop 57 of the memory selecting circuit 32 is set and thus the chip select signal CS2 is output. Therefore, after step S19, the game program data stored in the addresses "0100H-8000H" of the external ROM cartridge 16 can be read and executed. Thereafter, the internal ROM 30 is not selected and, therefore, it is not possible to access the same by way of CPU core 24.

I believe that the signal CS1 sets the "read enable" bit of the internal ROM chip, and CS2 sets the equivalent bit on the cartridge ROM. As these are on the same bus, the memory reads would simply be served by the chip that is activated for reading at any given time.

So would writing to address $FF50 set the chip select to permanently select the cartridge ROM?

If a specification says that FF50 controls the ROM chip select bit, I would assume that it works somewhat as follows:

CS1 = NOT (FF50 bit 0)
CS2 = FF50 bit 0

But I'm not a GB hardware expert nor have I read the specs, so I can't verify this off the top of my head.

It mentions nothing of $FF50. In no documentation is this address even mentioned except in very high-level overviews which explain that "writing $1 to $FF50 disabled the boot rom". It doesn't get into what the actual hardware / circuitry is doing.

Every other hardware address is documented except for this one.

It also appears that the address itself will have some bearing on whether or not the internal ROM is enabled. This is where things turn into I have no idea what is going on

As shown in FIG. 6, the memory selecting circuit 32 includes an RS flip-flop 57. A set input S of the RS flip-flop 57 receives an output of an AND gate 59 which receives three inputs including a signal DO, the write signal WR and a detecting signal, i.e., indicated the decoding of the address data "FF00H". The signal DO is the least significant bit of the data is stored in location "FF00H". The decoded signal of the address data "FF00H" is output from the address decoder 33 when an output of an AND gate (not shown) which detects that all bits A0-A7 of the address data are "0", that is, the least significant two digits in the hexadecimal representation are "00" and an output of an AND gate (not shown) which detects that all bits A8-A15 of the address data are "1", that is, the most significant two digits in the hexadecimal representation are "FF" are both output. The reset input R of the RS flip-flop 57 is coupled to the reset signal RES from the reset circuit 55 (FIG. 4). Then, the non-inverted output Q of the RS flip-flop 57 is applied to one input of an AND gate 63 through an inverter 61 and to one input of an OR gate 65. A decoded signal indicating address data "0000H"-00FFH" is applied to the other input of the AND gate 63. A decoded signal which corresponds to the few bytes (wherein the second character data is stored) starting at the address data "0100H" is applied to the other input of the OR gate 65. The decoded signal of the address data "0000H-00FFH" is the inversion of the bits A8-A15 of the address data being OR'ed. The decoded signal of the addresses from the address data "0100H" to the address corresponding to the number of bytes storing the second character data is the bits A8-A14 of the address data which are OR'ed. Then, an output of the OR gate 65 is used as an input to an AND gate 67 together with a decoded signal of the address "-7FFFH" which is the inversion of the bit A15 of the address data. The outputs of the two AND gates 63 and 67 become the aforementioned chip select signals CS1 and CS2, respectively.