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HD86

DX12 What do you do when you don't know in advance the total number of textures that will be used?

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I don't know in advance the total number of textures my app will be using. I wanted to use this approach but it turned out to be impractical because D3D11 hardware may not allow binding more than 128 SRVs to the shaders. Next I decided to keep all the texture SRV's in a default heap that is invisible to the shaders, and when I need to render a texture I would copy its SRV from the invisible heap to another heap that is bound to the pixel shader, but this also seems impractical because ID3D12Device::CopyDescriptorsSimple cannot be used in a command list. It executes immediately when it is called. I would need to close, execute and reset the command list every time I need to switch the texture.

What is the correct way to do this?

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Create texture atlases on the fly.  Page in and out only a subset of textures per frame to minimize bandwidth throttling.  It's not often you need (as in ever) 128 textures bound at one time.  You're free to upload quite a few (especially with D3D12/Vulkan using virtual memory, including system RAM/HDD). 

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If your understanding is correct you could limit your game to resource binding tier 2.

https://msdn.microsoft.com/en-us/library/windows/desktop/dn899127(v=vs.85).aspx

 

@SoldierOfLight  Could you clear this up, I am confused about this as well.  On tier 1 hardware can you still use dynamic indexing across the full descriptor heap.  Basically I don't understand tier 1 hardware and its relation to the descriptor heap.  If I have tier 1 hardware can the descriptor heap have more than 128 entries?  And if so can you use dynamic indexing across the entire heap?  I thought yes but wasn't sure...

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The restriction comes into play when looking at the root signature, not the descriptor heap. Binding tier 1 (which I think is only Haswell/Broadwell generation Intel chips at this point) means that any given shader stage cannot have more than 128 SRVs declared visible to it in the root signature. And since the root signature needs to declare a mapping for every resource visible to a shader, that means you can't have unbounded arrays declared in your shader.

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23 hours ago, SoldierOfLight said:

The restriction comes into play when looking at the root signature, not the descriptor heap. Binding tier 1 (which I think is only Haswell/Broadwell generation Intel chips at this point) means that any given shader stage cannot have more than 128 SRVs declared visible to it in the root signature. And since the root signature needs to declare a mapping for every resource visible to a shader, that means you can't have unbounded arrays declared in your shader.

Thanks SoldierOfLight, now that you state it outright, I had already seen that explanation before.

HD86 besides limiting your program to tier 2 you could also just not use dynamic indexing and bind and rebind like in older api's.

edit - ^ using descriptor tables.

Edited by Infinisearch

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