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etothex

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728 Good

About etothex

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  1. etothex

    Ouchy

    Aww, crud, they disabled hotlinking. I suppose I shouldn't have direct-linked though :)
  2. etothex

    Ouchy

    yeah, I can see how something like that wouldn't be pleasant to see (especially if you were younger at the time). I think everyone has some "incidents" in their lives that are traumatic, though auto accidents really are the worst. to cheer you up, considering your windows pains, and my procrastinaton during finals week, I have dug into my collection and brought up this which describes your situation quite well.
  3. etothex

    Wait, Not so Fast!

    Ahh, that makes more sense. As long as you know what you're doing :) Circuit design is very much an art and - like programming - it's easy to develop a personal style. My circuits teacher, really a god of digital design, insisted that everything be used in the way it is intended - clk goes to the CLK pin, /RESET goes to the set/reset pins, and everything else is done logically. Of course, I'm of the opinion that if it works, then don't fix it :)
  4. etothex

    Wait, Not so Fast!

    Just a few suggestions/questions: 1. Why are you gating the clock signals? Especially two layers of logic - that's just asking for a static logic hazard, which is death to a edge-triggered device. Sometimes it's necessary to gate inputs to CP, but I don't think this is a good scenario for that. 2. The state machine will wake up in an indeterminent state because you're not asynchronously clearing on reset. A better way would be to feed /Q into the first D input instead of Vdd. Of course this only works if your design can accept a synchronous clear instead of an asynchronous reset. All in all, looks good. I like your net naming (Maybe I should name some of my nets /CRAP?) :)
  5. etothex

    DMA is Good

    LOL, I wish you luck. I hate timers, I just got finished messing with synchronization for hours on end for a class project. It's just, dealing with both edge-sensitive and level-sensitive clocked devices, add in gated clocks, and asynchronous memory devices, and trying to make the whole mess work together and it's enough to make you want to say all right little chips, let's see how you like a 4GHZ clock, take that! *ahem* back to normal
  6. etothex

    DMA is Good

    I suppose I didn't look at it close enough, it looked like there were a bunch of floaters. :) I just turned in a huge circuits project today so any circuit looks awful right now. This is wayyy out of my field of expertise, but isn't the DMA supposed to assert /EOP when the transfer is complete? Or is that what you're saying and I'm just too out of it to see it? Or perhaps I'm just plain wrong? :)
  7. etothex

    DMA is Good

    I don't particularly like using my fingers when breadboarding, what you need to do is invest in a super pair of pliers that let you grab, poke, and prod to your heart's content :) It seems you've left a lot of pins floating - that can't be good can it?
  8. etothex

    Much better

    Not bad...looks like you've kept the area fairly tight :)
  9. etothex

    Switching to Hardware (Again)

    ohh yeah... there's no feeling quite like watching the first instruction execute is there? For a class I worked on a reduced version of the m68k chip - basically fewer registers and only capable of word-size instructions, not byte or long word - but it was still cool. How are you going about this? Simulation(in that case, what tool?), FPGA(cool), discrete TTL gates(if you're a glutton for punishment) or god forbid actually getting it fabbed?
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