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      Download the Game Design and Indie Game Marketing Freebook   07/19/17

      GameDev.net and CRC Press have teamed up to bring a free ebook of content curated from top titles published by CRC Press. The freebook, Practices of Game Design & Indie Game Marketing, includes chapters from The Art of Game Design: A Book of Lenses, A Practical Guide to Indie Game Marketing, and An Architectural Approach to Level Design. The GameDev.net FreeBook is relevant to game designers, developers, and those interested in learning more about the challenges in game development. We know game development can be a tough discipline and business, so we picked several chapters from CRC Press titles that we thought would be of interest to you, the GameDev.net audience, in your journey to design, develop, and market your next game. The free ebook is available through CRC Press by clicking here. The Curated Books The Art of Game Design: A Book of Lenses, Second Edition, by Jesse Schell Presents 100+ sets of questions, or different lenses, for viewing a game’s design, encompassing diverse fields such as psychology, architecture, music, film, software engineering, theme park design, mathematics, anthropology, and more. Written by one of the world's top game designers, this book describes the deepest and most fundamental principles of game design, demonstrating how tactics used in board, card, and athletic games also work in video games. It provides practical instruction on creating world-class games that will be played again and again. View it here. A Practical Guide to Indie Game Marketing, by Joel Dreskin Marketing is an essential but too frequently overlooked or minimized component of the release plan for indie games. A Practical Guide to Indie Game Marketing provides you with the tools needed to build visibility and sell your indie games. With special focus on those developers with small budgets and limited staff and resources, this book is packed with tangible recommendations and techniques that you can put to use immediately. As a seasoned professional of the indie game arena, author Joel Dreskin gives you insight into practical, real-world experiences of marketing numerous successful games and also provides stories of the failures. View it here. An Architectural Approach to Level Design This is one of the first books to integrate architectural and spatial design theory with the field of level design. The book presents architectural techniques and theories for level designers to use in their own work. It connects architecture and level design in different ways that address the practical elements of how designers construct space and the experiential elements of how and why humans interact with this space. Throughout the text, readers learn skills for spatial layout, evoking emotion through gamespaces, and creating better levels through architectural theory. View it here. Learn more and download the ebook by clicking here. Did you know? GameDev.net and CRC Press also recently teamed up to bring GDNet+ Members up to a 20% discount on all CRC Press books. Learn more about this and other benefits here.

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Found 34 results

  1. On Tuesday 25th July from 5:45pm, the Sydney Game Engine Developers will be holding their next Meetup in Ultimo. This month guest speakers Aidan Millott and Paulina Morrison Fell are joining forces to give a talk on Producing an Internal Engine. Producing engine technology that's shared across 10+ productions is no easy feat. Managing conflicting priorities from multiple games and coordinating shared development of features is only just a flavour of how challenging it can be. In this presentation, Aidan and Paulina share their experiences and techniques used to manage the distributed development of internal projects. Aidan Millott is an Area Product Owner at Wargaming.net, where he works with internal stakeholders to improve BigWorld, focusing on development of games by small teams. Prior to this, he was an Executive Producer and Studio Manager at Halfbrick studios, where he released 11 games on several platforms. Paulina Morrison Fell works at Wargaming.net as a Senior Project Manager. She works with the Client Engine team to manage the development of features for game productions, liaising with stakeholders from multiple studios. She has worked in a number of successful startups and bigger companies like Disney, where she has helped launch over 10 games for small platforms. Agenda for the night is: 5:45pm - Arrive and network (pizza and drinks provided) 6:15pm - Presentation by Aidan and Paulina 7:15pm - Network/Closing There are still spots available and we would love for you to join us for this interesting talk. RSVP and come along!
  2. It is good for programmers to understand what goes on inside a processor. The CPU is at the heart of our career. What goes on inside the CPU? How long does it take for one instruction to run? What does it mean when a new CPU has a 12-stage pipeline, or 18-stage pipeline, or even a "deep" 31-stage pipeline? Programs generally treat the CPU as a black box. Instructions go into the box in order, instructions come out of the box in order, and some processing magic happens inside. As a programmer, it is useful to learn what happens inside the box. This is especially true if you will be working on tasks like program optimization. If you don't know what is going on inside the CPU, how can you optimize for it? This article is about what goes on inside the x86 processor's deep pipeline. Stuff You Should Already Know First, this article assumes you know a bit about programming, and maybe even a little assembly language. If you don't know what I mean when I mention an instruction pointer, this article probably isn't for you. When I talk about registers, instructions, and caches, I assume you already know what they mean, can figure it out, or will look it up. Second, this article is a simplification of a complex topic. If you feel I have left out important details, please add them to the comments at the end. Third, I am focusing on Intel processors and the x86 family. I know there are many different processor families out there other than x86. I know that AMD introduced many useful features into the x86 family and Intel incorporated them. It is Intel's architecture and Intel's instruction set, and Intel introduced the most major feature being covered, so for simplicity and consistency I'm just going to stick with their processors. Fourth, this article is already out of date. Newer processors are in the works and some are due out in a few months. I am very happy that technology is advancing at a rapid pace. I hope that someday all of these steps are completely outdated, replaced with even more amazing advances in computing power. The Pipeline Basics From an extremely broad perspective the x86 processor family has not changed very much over its 35 year history. There have been many additions but the original design (and nearly all of the original instruction set) is basically intact and visible in the modern processor. The original 8086 processor has 14 CPU registers which are still in use today. Four are general purpose registers -- AX, BX, CX, and DX. Four are segment registers that are used to help with pointers -- Code Segment (CS), Data Segment (DS), Extra Segment (ES), and Stack Segment (SS). Four are index registers that point to various memory locations -- Source Index (SI), Destination Index (DI), Base Pointer (BP), and Stack Pointer (SP). One register contains bit flags. And finally, there is the most important register for this article: The Instruction Pointer (IP). The instruction pointer register is a pointer with a special job. The instruction pointer's job is to point to the next instruction to be run. All processors in the x86 family follow the same pattern. First, they follow the instruction pointer and decode the next CPU instruction at that location. After decoding, there is an execute stage where the instruction is run. Some instructions read from memory or write to it, others perform calculations or comparisons or do other work. When the work is done, the instruction goes through a retire stage and the instruction pointer is modified to point to the next instruction. This decode, execute, and retire pipeline pattern applies to the original 8086 processor as much as it applies to the latest Core i7 processor. Additional pipeline stages have been added over the years, but the pattern remains. What Has Changed Over 35 Years The original processor was simple by today's standard. The original 8086 processor began by evaluating the instruction at the current instruction pointer, decoded it, executed it, retired it, and moved on to the next instruction that the instruction pointer pointed to. Each new chip in the family added new functionality. Most chips added new instructions. Some chips added new registers. For the purposes of this article, I am focusing on the changes that affect the main flow of instructions through the CPU. Other changes like adding virtual memory or parallel processing are certainly interesting and useful, but not applicable to this article. In 1982 an instruction cache was added to the processor. Instead of jumping out to memory at every instruction, the CPU would read several bytes beyond the current instruction pointer. The instruction cache was only a few bytes in size, just large enough to fetch a few instructions, but it dramatically improved performance by removing round trips to memory every few cycles. In 1985, the 386 added cache memory for data as well as expanding the instruction cache. This gave performance improvements by reading several bytes beyond a data request. By this point both the instruction cache and data cache were measured in kilobytes rather than bytes. In 1989, the i486 moved to a five-stage pipeline. Instead of having a single instruction inside the CPU, each stage of the pipeline could have an instruction in it. This addition more than doubled the performance of a 386 processor of the same clock rate. The fetch stage extracted an instruction from the cache. (The instruction cache at this time was generally 8 kilobytes.) The second stage would decode the instruction. The third stage would translate memory addresses and displacements needed for the instruction. The fourth stage would execute the instruction. The fifth stage would retire the instruction, writing the results back to registers and memory as needed. By allowing multiple instructions in the processor at once, programs could run much faster. 1993 saw the introduction of the Pentium processor. The processor family changed from numbers to names as a result of a lawsuit--that's why it is Pentium instead of the 586. The Pentium chip changed the pipeline even more than the i486. The Pentium architecture added a second separate superscalar pipeline. The main pipeline worked like the i486 pipeline, but the second pipeline ran some simpler instructions, such as direct integer math, in parallel and much faster. In 1995, Intel released the Pentium Pro processor. This was a radically different processor design. This chip had several features including out-of-order execution processing core (OOO core) and speculative execution. The pipeline was expanded to 12 stages, and it included something termed a 'superpipeline' where many instructions could be processed simultaneously. This OOO core will be covered in depth later in the article. There were many major changes between 1995 when the OOO core was introduced and 2002 when our next date appears. Additional registers were added. Instructions that processed multiple values at once (Single Instruction Multiple Data, or SIMD) were introduced. Caches were introduced and existing caches enlarged. Pipeline stages were sometimes split and sometimes consolidated to allow better use in real-world situations. These and other changes were important for overall performance, but they don't really matter very much when it comes to the flow of data through the chip. In 2002, the Pentium 4 processor introduced a technology called Hyper-Threading. The OOO core was so successful at improving processing flow that it was able to process instructions faster than they could be sent to the core. For most users the CPU's OOO core was effectively idle much of the time, even under load. To help give a steady flow of instructions to the OOO core they attached a second front-end. The operating system would see two processors rather than one. There were two sets of x86 registers. There were two instruction decoders that looked at two sets of instruction pointers and processed both sets of results. The results were processed by a single, shared OOO core but this was invisible to the programs. Then the results were retired just like before, and the instructions were sent back to the two virtual processors they came from. In 2006, Intel released the "Core" microarchitecture. For branding purposes, it was called "Core 2" (because everyone knows two is better than one). In a somewhat surprising move, CPU clock rates were reduced and Hyper-Threading was removed. By slowing down the clock they could expand all the pipeline stages. The OOO core was expanded. Caches and buffers were enlarged. Processors were re-designed focusing on dual-core and quad-core chips with shared caches. In 2008, Intel went with a naming scheme of Core i3, Core i5, and Core i7. These processors re-introduced Hyper-Threading with a shared OOO core. The three different processors differed mainly by the size of the internal caches. Future Processors: The next microarchitecture update is currently named Haswell and speculation says it will be released late in 2013. So far the published docs suggest it is a 14-stage OOO core pipeline, so it is likely the data flow will still follow the basic design of the Pentium Pro. So what is all this pipeline stuff, what is the OOO core, and how does it help processing speed? CPU Instruction Pipelines In the most basic form described above, a single instruction goes in, gets processed, and comes out the other side. That is fairly intuitive for most programmers. The i486 has a 5-stage pipeline. The stages are - Fetch, D1 (main decode), D2 (secondary decode, also called translate), EX (execute), WB (write back to registers and memory). One instruction can be in each stage of the pipeline. There is a major drawback to a CPU pipeline like this. Imagine the code below. Back before CPU pipelines the following three lines were a common way to swap two variables in place. XOR a, b XOR b, a XOR a, b The chips starting with the 8086 up through the 386 did not have an internal pipeline. They processed only a single instruction at a time, independently and completely. Three consecutive XOR instructions is not a problem in this architecture. We'll consider what happens in the i486 since it was the first x86 chip with an internal pipeline. It can be a little confusing to watch many things in motion at once, so you may want to refer back to the diagram above. The first instruction enters the Fetch stage and we are done with that step. On the next step the first instruction moves to D1 stage (main decode) and the second instruction is brought into fetch stage. On the third step the first instruction moves to D2 and the second instruction gets moved to D1 and another is fetched. On the next stage something goes wrong. The first instruction moves to EX ... but other instructions do not advance. The decoder stops because the second XOR instruction requires the results of the first instruction. The variable (a) is supposed to be used by the second instruction, but it won't be written to until the first instruction is done. So the instructions in the pipeline wait until the first instruction works its way through the EX and WB stages. Only after the first instruction is complete can the second instruction make its way through the pipeline. The third instruction will similarly get stuck, waiting for the second instruction to complete. This is called a pipeline stall or a pipeline bubble. Another issue with pipelines is some instructions could execute very quickly and other instructions would execute very slowly. This was made more visible with the Pentium's dual-pipeline system. The Pentium Pro introduced a 12-stage pipeline. When that number was first announced there was a collective gasp from programmers who understood how the superscalar pipeline worked. If Intel followed the same design with a 12-stage superscalar pipeline then a pipeline stall or slow instruction would seriously harm execution speed. At the same time they announced a radically different internal pipeline, calling it the Out Of Order (OOO) core. It was difficult to understand from the documentation, but Intel assured developers that they would be thrilled with the results. Let's have a look at this OOO core pipeline in more depth. The Out Of Order Core Pipeline The OOO Core pipeline is a case where a picture is worth a thousand words. So let's get some pictures. Diagrams of CPU Pipelines The i486 had a 5-stage pipeline that worked well. The idea was very common in other processor families and works well in the real world. The Pentium pipeline was even better than the i486. It had two instruction pipelines that could run in parallel, and each pipeline could have multiple instructions in different stages. You could have nearly twice as many instructions being processed at the same time. Having fast instructions waiting for slow instructions was still a problem with parallel pipelines. Having sequential instruction order was another issue thanks to stalls. The pipelines are still linear and can face a performance barrier that cannot be breached. The OOO core is a huge departure from the previous chip designs with their linear paths. It added some complexity and introduced nonlinear paths: The first thing that happens is that instructions are fetched from memory into the processor's instruction cache. The decoder on the modern processors can detect when a large branch is about to happen (such as a function call) and can begin loading the instructions before they are needed. The decoding stage was modified slightly from earlier chips. Instead of just processing a single instruction at the instruction pointer, the Pentium Pro processor could decode up to three instructions per cycle. Today's (circa 2008-2013) processors can decode up to four instructions at once. Decoding produces small fragments of operations called micro-ops or u-ops. Next is a stage (or set of stages) called micro-op translation, followed by register aliasing. Many operations are going on at once and we will potentially be doing work out of order, so an instruction could read to a register at the same time another instruction is writing to it. Writing to a register could potentially stomp on a value that another instruction needs. Inside the processor the original registers (such as AX, BX, CX, DX, and so on) are translated (or aliased) into internal registers that are hidden from the programmer. The registers and memory addresses need to have their values mapped to a temporary value for processing. Currently 4 micro-ops can go through translation every cycle. After micro-op translation is complete, all of the instruction's micro-ops enter a reorder buffer, or ROB. The ROB currently holds up to 128 micro-ops. On a processor with Hyper-Threading the ROB can also coordinate entries from multiple virtual processors. Both virtual processors come together into a single OOO core at the ROB stage. These micro-ops are now ready for processing. They are placed in the Reservation Station (RS). The RS currently can hold 36 micro-ops at any one time. Now the magic of the OOO core happens. The micro-ops are processed simultaneously on multiple execution units, and each execution unit runs as fast as it can. Micro-ops can be processed out of order as long as their data is ready, sometimes skipping over unready micro-ops for a long time while working on other micro-ops that are ready. This way a long operation does not block quick operations and the cost of pipeline stalls is greatly reduced. The original Pentium Pro OOO core had six execution units: two integer processors, one floating-point processor, a load unit, a store address unit, and a store data unit. The two integer processors were specialized; one could handle the complex integer operations, the other could solve up to two simple operations at once. In an ideal situation the Pentium Pro OOO Core execution units could process seven micro-ops in a single clock cycle. Today's OOO core still has six execution units. It still has the load address, store address, and store data execution units, the other three have changed somewhat. Each of the three execution units Today's OOO core still has six execution units. It still has the load address, store address, and store data execution units, the other three have changed somewhat. Each of the three execution units perform basic math operations, or instead they perform a more complex micro-op. Each of the three execution units are specialized to different micro-ops allowing them to complete the work faster than if they were general purpose. In an ideal situation today's OOO core can process 11 micro-ops in a single cycle. Eventually the micro-op is run. It goes through a few more small stages (which vary from processor to processor) and eventually gets retired. At this point it is returned back to the outside world and the instruction pointer is advanced. From the program's point of view the instruction has simply entered the CPU and exited the other side in exactly the same way it did back on the old 8086. If you were following carefully you may have noticed one very important issue in the way it was just described. What happens if there is a change in execution location? For example, what happens when the code hits an 'if' statement or a 'switch" statement? On the older processors this meant discarding the work in the superscalar pipeline and waiting for the new branch to begin processing. A pipeline stall when the CPU holds one hundred instructions or more is an extreme performance penalty. Every instruction needs to wait while the instructions at the new location are loaded and the pipeline restarted. In this situation the OOO core needs to cancel work in progress, roll back to the earlier state, wait until all the micro-ops are retired, discard them and their results, and then continue at the new location. This was a very difficult problem and happened frequently in the design. The performance of this situation was unacceptable to the engineers. This is where the other major feature of the OOO core comes in. Speculative execution was their answer. Speculative execution means that when a conditional statement (such as an 'if' block) is encountered the OOO core will simply decode and run all the branches of the code. As soon as the core figures out which branch was the correct one, the results from the unused branches would be discarded. This prevents the stall at the small cost of running the code inside the wrong branch. The CPU designers also included a branch prediction cache which further improved the results when it was forced to guess at multiple branch locations. We still have CPU stalls from this problem, but the solutions in place have reduced it to the point where it is a rare exception rather than a usual condition. Finally, CPUs with Hyper-Threading enabled will expose two virtual processors for a single shared OOO core. They share a Reorder Buffer and OOO core, appearing as two separate processors to the operating system. That looks like this: A processor with Hyper-Threading gives two virtual processors which in turn gives more data to the OOO core. This gives a performance increase during general workloads. A few compute-intensive workflows that are written to take advantage of every processor can saturate the OOO core. During those situations Hyper-Threading can slightly decrease overall performance. Those workflows are relatively rare; Hyper-Threading usually provides consumers with approximately double the speed they would see for their everyday computer tasks. An Example All of this may seem a little confusing. Hopefully an example will clear everything up. From the application's perspective, we are still running on the same instruction pipeline as the old 8086. There is a black box. The instruction pointed to by the instruction pointer is processed by the black box, and when it comes out the results are reflected in memory. From the instruction's point of view, however, that black box is quite a ride. Here is today's (circa 2008-2013) CPU ride, as seen by an instruction: First, you are a program instruction. Your program is being run. You are waiting patiently for the instruction pointer to point to you so you can be processed. When the instruction pointer gets about 4 kilobytes away from you -- about 1500 instructions away -- you get collected into the instruction cache. Loading into the cache takes some time, but you are far away from being run. This prefetch is part of the first pipeline stage. The instruction pointer gets closer and closer. When the instruction pointer gets about 24 instructions away, you and five neighbors get pulled into the instruction queue. This processor has four decoders. It has room for one complex instruction and up to three simple instructions. You happen to be a complex instruction and are decoded into four micro-ops. Decoding is a multi-step process. Part of the decode process involved a scan to see what data you need and if you are likely to cause a jump to somewhere new. The decoder detected a need for some additional data. Unknown to you, somewhere on the far side of the computer, your data starts getting loaded into the data cache. Your four micro-ops step up to the register alias table. You announce which memory address you read from (it happens to be fs:[eax+18h]) and the chip translates that into temporary addresses for your micro-ops. Your micro-ops enter the reorder buffer, or ROB. At the first available opportunity they move to the Reservation Station. The Reservation Station holds instructions that are ready to be run. Your third micro-op is immediately picked up by Execution Port 5. You don't know why it was selected first, but it is gone. A few cycles later your first micro-op rushes to Port 2, the Load Address execution unit. The remaining micro-ops wait as various ports collect other micro-ops. They wait as Port 2 loads data from the memory cache and puts it in temporary memory slots. They wait a long time... A very long time... Other instructions come and go while they wait for their micro-op friend to load the right data. Good thing this processor knows how to handle things out of order. Suddenly both of the remaining micro-ops are picked up by Execution Ports 0 and 1. The data load must be complete. The micro-ops are all run, and eventually the four micro-ops meet back in the Reservation Station. As they travel back through the gate the micro-ops hand in their tickets listing their temporary addresses. The micro-ops are collected and joined, and you, as an instruction, feel whole again. The CPU hands you your result, and gently directs you to the exit. There is a short line through a door marked "Retirement". You get in line, and discover you are standing next to the same instructions you came in with. You are even standing in the same order. It turns out this out-of-order core really knows its business. Each instruction then goes out of the CPU, seeming to exit one at a time, in the same order they were pointed to by the instruction pointer. Conclusion This little lecture has hopefully shed some light on what happens inside a CPU. It isn't all magic, smoke, and mirrors. Getting back to the original questions, we now have some good answers. What goes on inside the CPU? There is a complex world where instructions are broken down into micro-operations, processed as soon as possible in any order, then put back together in order and in place. To an outsider it looks like they are being processed sequentially and independently. But now we know that on the inside they are handled out of order, sometimes even running braches of code based on a prediction that they will be useful. How long does it take for one instruction to run? While there was a good answer to this in the non-pipelined world, in today's processors the time it takes is based on what instructions are nearby, and the size and contents of the neighboring caches. There is a minimum amount of time it takes to go through the processor, but that is roughly constant. A good programmer and optimizing compiler can make many instructions run in around amortized zero time. With an amortized zero time it is not the cost of the instruction that is slow; instead it means it takes the time to work through the OOO core and the time to wait for cache memory to load and unload. What does it mean when a new CPU has a 12-stage pipeline, or 18-stage, or even a "deep" 31-stage pipeline? It means more instructions are invited to the party at once. A very deep pipeline can mean that several hundred instructions can be marked as 'in progress' at once. When everything is going well the OOO core is kept very busy and the processor gains an impressive throughput of instructions. Unfortunately, this also means that a pipeline stall moves from being a mild annoyance like it was in the early days, to becoming a performance nightmare as hundreds of instructions need to wait around for the pipeline to clear out. How can I apply this to my programs? The good news is that CPUs can anticipate most common patterns, and compilers have been optimizing for OOO core for nearly two decades. The CPU runs best when instructions and data are all in order. Always keep your code simple. Simple and straightforward code will help the compiler's optimizer identify and speed up the results. Don't jump around if you can help it, and if you need to jump, try to jump around exactly the same way every time. Complex designs like dynamic jump tables are fancy and can do a lot, but neither the compiler or CPU will predict what will be coming up, so complex code is very likely to result in stalls and mis-predictions. On the other side, keep your data simple. Keep your data in order, adjacent, and consecutive to prevent data stalls. Choosing the right data structures and data layouts can do much to encourage good performance. As long as you keep your code and data simple you can generally rely on your compiler's optimizer to do the rest. Thanks for joining me on the ride. If you enjoyed this article, you might also enjoy Keith O'Conor's look at 'GPU Performance for Game Artists'. Updates 2013-05-17 Removed a word that someone was offended by
  3. Introduction Many of the beginners on the site are pre-college students. Often beginners will learn by reading tutorials on the Internet, copying code from books, and trying out things that they find interesting. This article is part of a series that focuses on giving pre-college developers the basics they need to understand data structures. The previous article was on Stacks and Queues. This article is about tree data structures. Tree Data Structures Trees of data are very useful for many things. Since we are a game development site, one of the most common uses of tree data structures is to subdivide space, allowing the developer to quickly find objects that are nearby without having to check every object in the game world. Even though tree data structures are fundamental to computer science, in practice most standard libraries do not directly include tree-based containers. I'll cover the reasons for that in the details. The Basic Tree A tree is, well, a tree. A real life tree has a root. It has branches. And at the end of the branches it has leaves. A data structure tree starts at a root node. Each node can branch off into child nodes. If a node has no children, it is called a leaf node. When you have more than one tree, it is called a forest. Here is an example of a tree. They are generally drawn upside down from real life trees; the root node is usually drawn at the top, and the leaves are usually drawn at the bottom. One of the first questions to ask is: How many children should a node have? Many trees have up to two child nodes. These are called binary trees. The example above is a binary tree. Usually the children are called the left and right child nodes. Another common type of tree in games has four child nodes. A quadtree, which is a tree that can be used to cover a grid, will usually call the child nodes by the direction they cover: NorthWest or NW, NorthEast or NE, SouthWest or SW, and SouthEast or SE. Trees are used in many algorithms. You have already heard about binary trees. There are balanced trees and unbalanced trees. There are red-black trees, AVL trees, and many more. While the theory of a tree is nice, it suffers from some major flaws: Storage space and access speed. What is the best way to store a tree? The most basic route, simply building a linked list, is also one of the worst cases you can construct. Let's assume you want to build a balanced binary tree. You start out with this data structure: // Tree node Node* left; Node* right; sometype data; Fair enough. Now let's assume you want to store 1024 items in it. So for 1024 nodes you will need to store 2048 pointers. That's fine, pointers are small and you can live with the tiny space. You may recall that every time you allocate an object it consumes a small amount of additional resources. The exact amount of extra resources depends on the libraries your languge is using. Many popular compilers and tools can use the wide range from just a few bytes to store the data on the small end up to using several kilobytes of padding to help with debugging on the large end. I have worked with systems where even the smallest allocation required 4KB of memory; in this case the 1024 items would require about 4MB of memory. It usually isn't that bad, but the overhead of lots of tiny objects allocated individually will add up quickly. Next, the speed issue. Processors like it when things are right next to each other in memory. Modern processors have a piece of very fast memory --- the cache --- that usually works really well for most data. Whenever a program needs one piece of data the cache will load up that item and also all the items next to it. When something isn't loaded in the very fast memory --- called a cache miss --- it will pause the program until the data is loaded. The most direct format where every tree item is stored in its own little bucket of memory means that nothing is next to each other. Every time you travel across the tree you end up stalling your program. So if making a tree directly has these problems, we should consider a data structure that acts like a tree but doesn't have the problems. Which brings us to... The Heap Just to be confusing, there are two kinds of heap. One is the memory heap. It is a huge block of memory where objects live. That is not the kind of heap I am writing about. A heap data structure in concept is the same as a tree. It has a root node, each node has child nodes, and so on. A heap adds constraints that it must always be sorted in a special way. You will need to provide a sorting function --- usually the less than operator. When objects are added or removed from a heap the structure shuffles itself to be a "complete" tree, where every level in the tree is full, except for possibly the last row where everything must be pushed on one side. This makes storage space and searches on a heap very efficient. Heaps can be stored in an array or a dynamic array so there is little space wasted per allocation. C++ provides functions such as push_heap() and pop_heap() to help you implement heaps on your own containers. Java and C# do not provide similar functionality in their standard libraries. Here are a tree and a heap with the same information: Why They Are Not In Standard Libraries These are basic, fundamental, very useful data structures. Many people believe they should be included in standard libraries. A few seconds on your favorite search engine will find thousands of implementations of trees. It turns out that while trees are very useful and fundamental, there are better containers out there. There are more complex data structures that have the benefits of a tree (stability and shape) and the benefits of a heap (space and speed). The more advanced data structures are generally a combination of data tables coupled with lookup tables. The two tables combined will allow fast access, fast modification, and will perform well in both dense and sparse situations. They don't require shuffling items around when items are added or removed, and they don't consume excess memory or fragment memory after extended use. Conclusion It is important to know about the tree data structures since you will rely on them many times in your career. Also important is that using these data structures directly has a few drawbacks. You can implement your own tree structures, just be aware that more compact representations exist. So why did I cover these if they aren't really used in standard libraries? They are used as the internals to the next topic: NEXT: Non-Linear Data Structures RELATED READING: Introduction to Octrees
  4. Introduction Many of the beginners on the site are pre-college students. Often beginners will learn by reading tutorials on the Internet, copying code from books, and trying out things that they find interesting. This article is part of a series that focuses on giving pre-college developers the basics they need to understand data structures. The previous article was Arrays, Dynamic Arrays, and Linked Lists. This article is about stacks and queues. The Stack Imagine you have a bunch of papers. You push one paper onto the stack. Now you can only easily access the top paper. You push another paper onto the stack. The earlier paper is now covered and inaccessible, and the new paper is available for use. When you are done with the top paper you can remove it from the stack, exposing the one beneath. That is the idea of a stack. A stack is a LIFO structure. That stands for Last In First Out. When you add and remove from a stack, the last one that you put in will be the first one you get out. There are really only three operations needed for a stack: Push, Pop, and Top. Push will add an object to the stack. Pop will remove an object from the stack. Top will give you the last-most object on the stack. These containers are part of the standard libraries of most languages. In C++ it is called a stack. In Java and C# it is a Stack. (Yes, the only difference is the capitalization of the first letter.) Under the hood, a stack is often implemented as a dynamic array. If you recall from that data structure, the fastest operations on a dynamic array are to add and remove elements from the end. Since a stack is always adding and removing from the end, it is usually extremely fast to push and pop objects onto a stack. The Queue Imagine you are waiting in line for something. The first person in the line gets served, then leaves. The second person in line gets served, then leaves. More people walk over to the line and stand at the end of it. That is the idea of a queue. A queue is a FIFO structure. That stands for First In First Out. When you add and remove from a queue, the first one you put in will be the first one you get out. A queue only needs a few operations: Push_Back, Pop_Front, Front, and Back. Push_Back will add to the end of the queue. Pop_Front will remove from the front of the queue. Front and Back will let you examine the two ends of a queue. Programmers will frequently need to add and remove from both ends of a queue. This is called a double ended queue, or deque. In this case they add two other operations, Push_Front and Pop_Back. Again, these containers are included in most major languages. In C++ it is a queue and a deque. Java specifies interfaces for both queue and deque, then relies on a LinkedList for the implementation. C# provides a Queue class, but not a Deque class. Internally, a queue and a double-ended queue can be somewhat complex. Since objects can come and go at either end, the internal container needs to be able to grow and shrink at the beginning and at the end. Many implementations will rely on multiple pages of memory. When either end grows beyond the current page, an extra page is added. Similarly a page is removed when it is no longer needed. Java follows a different route; it requires a little additional memory using a linked list rather than pages of memory, but it works for the language. Priority Queue There is a very common variation on the queue. A priority queue is very similar to a basic queue. You push things on to the end, and you pop things off from the front. The difference is that you can give priority to certain items in the queue. All of the most important items are processed in a FIFO order. Then the next priority items are processed in a FIFO order. Repeat until the lowest priority items are handled in FIFO order. If you add a new item that is higher priority than the rest of the queue, it will immediately jump to the head of the line. In C++ this is called a priority_queue. In Java it is a PriorityQueue. C# does not include a priority queue in the standard library. Priority queues are not just useful in getting yourself to the front of the line on the corporate printer. Priority queues can be used to easily implement algorithms like the A-star searching routine. The most likely results can be given a higher priority over the less likely results. You could choose to build your own system for sorting and organizing your A-star search, but it will be much easier to just use the built-in priority queue. Conclusion Stacks and queues and deques and priority queues can be implemented in terms of other data structures. They are not fundamental data structures, but they are frequently used. They are very efficient when you need to work only with the endpoints of your data, and don't really care what is in the middle. NEXT: Trees and Heaps Updates: 2013-04-01 Typo
  5. Introduction Many of the beginners on the site are pre-college students. Often beginners will learn by reading tutorials on the Internet, copying code from books, and trying out things that they find interesting. This article is part of a series that focuses on giving pre-college developers the basics they need to understand data structures. This article is about the first three basic data structures: the array; the dynamic array; and the linked list. The Array When you need one object, you create one object. When you need several objects... well, you have several options. I have seen many beginners with code like the following: // High Scores int score1 = 0; int score2 = 0; int score3 = 0; int score4 = 0; int score5 = 0; This gives you five high score values. This method works just fine until you need fifty or a hundred or a thousand of something. Rather than creating your objects individually you can use an array. // High Scores const int NUM_HIGH_SCORES = 5; int highScore[NUM_HIGH_SCORES] = {0}; This will create a buffer of 5 items, like so: Note that the array index starts at zero. If you have five items, then they range from zero to four. Drawbacks of a Simple Array If all you want is a fixed number of objects an array can work just fine. Let's say you want to add an item to the array. You can't do that with a simple array. Let's say you want to remove an item from the array. You can't do that with with a simple array. You are stuck with the same size of items for the duration of the object. What we need is an array that can change size. This brings us to... The Dynamic Array A dynamic array is an array that can change sizes. Major languages support dynamic arrays in their standard libraries. In C++ it is a vector. In Java it is an ArrayList. In C# it is a List. All of these are dynamic arrays. Under the hood a dynamic array is a simple array, but it also has two extra pieces of data. It stores how big the simple array actually is, and it stores how much data the simple array can actually store. A dynamic array might look something like this: // Internals of a dynamic array class sometype *internalArray; unsigned int currentLength; unsigned int maxCapacity; he internalArray member points to a dynamically allocated buffer. That actual size of the buffer is stored in maxCapacity. The number of items actually used is represented with currentLength. Adding to a Dynamic Array When you add an object to a dynamic array several things happen. The array class verifies that there is enough space. If currentLength < maxCapacity then there is room to add to the array. If there is not enough space then a larger internal array is allocated, and everything is copied over to th new internal array. The maxCapacity value is increased to the new larger size. When there is enough space, the new item is added. Every element after the insertion point must be copied over one space in the internal array, and after the copies are made then the hole is filled with your new object, then the currentLength value is incremented. Since every object after the insertion point must be moved, the best case is when you add to the end; zero objects must be moved (unless the internal array must be expanded). A dynamic array works best when you only add to the end rather than adding to the middle. When you add an object to a dynamic array it is possible for every object to move in memory. For languages like C and C++, adding to a dynamic array means ALL pointers to array objects become invalid. Removing from a Dynamic Array Removing objects is less work than adding objects. First, the object itself is destroyed. Second, every object after that location is moved over one space. Finally, the currentLength is decreased. Just like adding to the end of the array, removing from the end of the array is the best case because zero objects need to be moved. Also note that we don't need to resize the internal array to make it smaller. The space can hang around in case we add objects later. Removing an object to a dynamic array causes everything after the removed item to move in memory. For languages like C and C++, removing from a dynamic array means pointers to everything after the removed object become invalid. Drawbacks of Dynamic Arrays Let's say your array is very large, and you need to add and remove objects frequently. This can cause objects to be frequently copied to new locations, and it can cause many pointers to be invalidated. If you need to make frequent changes in the middle of a dynamic array, there is a better type of linear data structure for you... Linked Lists An array is a continuous block of memory, each item after the other. A linked list is a chain of objects. Again, the major languages have linked lists in their standard libraries. In C++ it is called a list. In Java and C# it is called a LinkedList. A linked list is made of a series of nodes. Each node is basically made like this: // Linked list node sometype data; Node* next; That generates this type of structure: Each node chains to the next. Adding to a Linked List When an object is added to a linked list it starts by creating a new node. Your data is copied inside the node. Next, the insertion point is found. The new node's pointer to the next object is updated to point to the node that will follow it. Finally, the node before the new node is modified to point to your new node. Removing From a Linked List When an object is removed from a linked list, the node before the removed node is found. It is altered to point to the removed object's next node. Then the removed object can be safely deleted. Benefits of a Linked List The biggest benefit of a linked list comes when adding and removing objects from the list. Making changes to the middle of the list is very quick. Remember that a dynamic array potentially caused every item to move, a linked list keeps every other object in place. Drawbacks of a Linked List Recall that a dynamic array is a continuous block of memory. If you need to get the 500th item in the array the code can simply look 500 spaces ahead. In a linked list the memory is chained together. If you need to find the 500th item, you must start at the beginning of the chain and follow its pointer to the next item. Then you need to follow the pointer in the next node. Then you need to follow the pointer in the next node. Repeat 500 times. Random access to a linked list is very slow. The other major drawback of a linked list isn't quite as obvious. Each node requires a little extra space. How much space does it require? You might think it only requires the size of a pointer, but that isn't quite right. There is a little bit of overhead every time an object is created dynamically. Some languages, like C++, work with pages of memory. Typically a page is 4 kilobytes. When you use the default new and delete operators a full page of memory will be allocated even if you will only use a single byte. Both Java and C# were designed differently and have special rules for small objects. These languages do not require a full 4kB memory page, but they do have a small amount of overhead. You don't need to worry about the second drawback if you are using the standard libraries. They have been written in a way that minimizes the wasted space. Conclusion These three types, the array, dynamic array, and linked list, form the basis for nearly all the more complex data containers. When you get to college some of the first assignments in a data structures class will be to implement a dynamic array and a linked list class on your own. These structures are fundamental to programming. It doesn't matter what language you learn, you will be using them to work with your data. NEXT: Stacks and Queues Updates 2013-03-29 - typos.
  6. Hello everyone, This is my first time posting here, but I've been following for a while. I am finishing my last term in college before getting my Bachelor's in Game Programming and Development. I have always been interested in level design, and I'm hoping to find a job in this area once I'm done. My question is, how should I go about breaking into this field within the industry? I have a little experience with developing game levels in Unreal; 2D Platformers, but not much else. Should I keep focusing on creating levels in game engines, or are level schematics/maps a good way to demonstrate skills too?
  7. GameDev.net and CRC Press have teamed up to bring a new ebook of content curated from top titles published by CRC Press. The freebook, Practices of Game Design & Indie Game Marketing, includes chapters from The Art of Game Design: A Book of Lenses, A Practical Guide to Indie Game Marketing, and An Architectural Approach to Level Design. The GameDev.net FreeBook is relevant to game designers, developers, and those interested in learning more about the challenges in game development. We know game development can be a tough discipline and business, so we picked several chapters from CRC Press titles that we thought would be of interest to you, the GameDev.net audience, in your journey to design, develop, and market your next game. The free ebook is available through CRC Press by clicking here. The Curated Books The Art of Game Design: A Book of Lenses, Second Edition, by Jesse Schell Presents 100+ sets of questions, or different lenses, for viewing a game’s design, encompassing diverse fields such as psychology, architecture, music, film, software engineering, theme park design, mathematics, anthropology, and more. Written by one of the world's top game designers, this book describes the deepest and most fundamental principles of game design, demonstrating how tactics used in board, card, and athletic games also work in video games. It provides practical instruction on creating world-class games that will be played again and again. View it here. A Practical Guide to Indie Game Marketing, by Joel Dreskin Marketing is an essential but too frequently overlooked or minimized component of the release plan for indie games. A Practical Guide to Indie Game Marketing provides you with the tools needed to build visibility and sell your indie games. With special focus on those developers with small budgets and limited staff and resources, this book is packed with tangible recommendations and techniques that you can put to use immediately. As a seasoned professional of the indie game arena, author Joel Dreskin gives you insight into practical, real-world experiences of marketing numerous successful games and also provides stories of the failures. View it here. An Architectural Approach to Level Design This is one of the first books to integrate architectural and spatial design theory with the field of level design. The book presents architectural techniques and theories for level designers to use in their own work. It connects architecture and level design in different ways that address the practical elements of how designers construct space and the experiential elements of how and why humans interact with this space. Throughout the text, readers learn skills for spatial layout, evoking emotion through gamespaces, and creating better levels through architectural theory. View it here. Learn more and download the ebook by clicking here. Did you know? GameDev.net and CRC Press also recently teamed up to bring GDNet+ Members up to a 20% discount on all CRC Press books. Learn more about this and other benefits here.
  8. GameDev.net and CRC Press have teamed up to bring a new ebook of content curated from top titles published by CRC Press. The freebook, Practices of Game Design & Indie Game Marketing, includes chapters from The Art of Game Design: A Book of Lenses, A Practical Guide to Indie Game Marketing, and An Architectural Approach to Level Design. The GameDev.net FreeBook is relevant to game designers, developers, and those interested in learning more about the challenges in game development. We know game development can be a tough discipline and business, so we picked several chapters from CRC Press titles that we thought would be of interest to you, the GameDev.net audience, in your journey to design, develop, and market your next game. The free ebook is available through CRC Press by clicking here. The Curated Books The Art of Game Design: A Book of Lenses, Second Edition, by Jesse Schell Presents 100+ sets of questions, or different lenses, for viewing a game’s design, encompassing diverse fields such as psychology, architecture, music, film, software engineering, theme park design, mathematics, anthropology, and more. Written by one of the world's top game designers, this book describes the deepest and most fundamental principles of game design, demonstrating how tactics used in board, card, and athletic games also work in video games. It provides practical instruction on creating world-class games that will be played again and again. View it here. A Practical Guide to Indie Game Marketing, by Joel Dreskin Marketing is an essential but too frequently overlooked or minimized component of the release plan for indie games. A Practical Guide to Indie Game Marketing provides you with the tools needed to build visibility and sell your indie games. With special focus on those developers with small budgets and limited staff and resources, this book is packed with tangible recommendations and techniques that you can put to use immediately. As a seasoned professional of the indie game arena, author Joel Dreskin gives you insight into practical, real-world experiences of marketing numerous successful games and also provides stories of the failures. View it here. An Architectural Approach to Level Design This is one of the first books to integrate architectural and spatial design theory with the field of level design. The book presents architectural techniques and theories for level designers to use in their own work. It connects architecture and level design in different ways that address the practical elements of how designers construct space and the experiential elements of how and why humans interact with this space. Throughout the text, readers learn skills for spatial layout, evoking emotion through gamespaces, and creating better levels through architectural theory. View it here. Learn more and download the ebook by clicking here. Did you know? GameDev.net and CRC Press also recently teamed up to bring GDNet+ Members up to a 20% discount on all CRC Press books. Learn more about this and other benefits here. View full story
  9. Hi, community. I am writing a series of articles about Lighting related with real-time computer graphics. The purpose is to get information from a lot of great resources like computer graphics books, blogs, and forums, and try to explain them as easy and clear as I can. I am going to update the list periodically. Lighting Series The first post in the list is the following Lighting Series Part 1 - Light and Radiometry Update (2017.07.05) Lighting Series Part 2 - Radiant Energy and Radiant Power Update (2017.07.16) Lighting Series Part 3 - Radiance All suggestions for improvements, corrections, and new topics, are very welcome because in this way I am going to learn a lot and, and why not, maybe this helps anybody with the same doubts than me. Hope you find this useful!
  10. A PDF document collating John Carmack's .plan from 2007. The .plan was used as an early form of the developer blog. Download PDF: click here
  11. A PDF document collating John Carmack's .plan from 2006. The .plan was used as an early form of the developer blog. Download PDF: click here
  12. A PDF document collating John Carmack's .plan from 2001. The .plan was used as an early form of the developer blog. Download PDF: click here
  13. A PDF document collating John Carmack's .plan from 2004. The .plan was used as an early form of the developer blog. Download PDF: click here
  14. A PDF document collating John Carmack's .plan from 2001. The .plan was used as an early form of the developer blog. Download PDF: click here
  15. A PDF document collating John Carmack's .plan from 2002. The .plan was used as an early form of the developer blog. PDF: click here
  16. A PDF document collating John Carmack's .plan from 1999, covering topics from OpenGL and D3D to Quake. The .plan was used as an early form of the developer blog. Download PDF: click here
  17. A PDF document collating John Carmack's .plan from 1999, covering topics from OpenGL and D3D to Quake. The .plan was used as an early form of the developer blog. Download PDF: click here
  18. A PDF document collating John Carmack's .plan from 1998. The .plan was used as an early form of the developer blog. Download PDF: johnc-plan_1998.pdf
  19. A PDF document collating John Carmack's .plan from 1997. The .plan was used as an early form of the developer blog. Download PDF: click here
  20. A PDF document collating John Carmack's .plan from 1996, covering topics from OpenGL and D3D to Quake. The .plan was used as an early form of the developer blog. Download PDF: click here
  21. A PDF document collating John Carmack's .plan from 2001. The .plan was used as an early form of the developer blog. Download PDF: click here
  22. AbleGamers Foundation, the charity and organization wielding the power of gaming to break down the barriers of economic and social isolation for people with disabilities, has announced Player Panels, a new initiative which partners AbleGamers and its community with leading publishers, AAA to indie developers and leading researchers to ensure game accessibility is at the forefront of game development. Steve Spohn, AbleGamers COO shared: Working with the University of York, AbleGamers’ Player Panels enlists gamers with disabilities to work with video game companies and researchers directly to help lead the charge in improved accessibility technologies and game design practices. Player Panels team members will leverage their personal challenges (due to their various disabilities) faced while playing games, helping enhance and shape and the future of game accessibility based on real-world, first-hand experiences. “For the last 12 years, AbleGamers’ in-house accessibility experts have provided game companies with critical input through our game accessibility reviews and Includification resources,” said Christopher Power, Vice President of AbleGamers and Lecturer at the University of York. “Player Panels is the natural progression of that program. All of our testers live with disabilities, which allows them to offer the game industry in-depth insight to potential solutions that may not be apparent to people who have studied, but have not experienced disability firsthand.” AbleGamers’ Player Panels will connect disabled gamers and top organizations that share the mutual goal of making sure as many people as possible can game regardless of their disability. Player Panels team member qualifications only require a love of video games and some form of disability. Those approved will be compensated for their time and expertise. Gamers with disabilities who are interested in joining can sign up today at www.ablegamers.org/player-panels.
  23. AbleGamers Foundation, the charity and organization wielding the power of gaming to break down the barriers of economic and social isolation for people with disabilities, has announced Player Panels, a new initiative which partners AbleGamers and its community with leading publishers, AAA to indie developers and leading researchers to ensure game accessibility is at the forefront of game development. Steve Spohn, AbleGamers COO shared: Working with the University of York, AbleGamers’ Player Panels enlists gamers with disabilities to work with video game companies and researchers directly to help lead the charge in improved accessibility technologies and game design practices. Player Panels team members will leverage their personal challenges (due to their various disabilities) faced while playing games, helping enhance and shape and the future of game accessibility based on real-world, first-hand experiences. “For the last 12 years, AbleGamers’ in-house accessibility experts have provided game companies with critical input through our game accessibility reviews and Includification resources,” said Christopher Power, Vice President of AbleGamers and Lecturer at the University of York. “Player Panels is the natural progression of that program. All of our testers live with disabilities, which allows them to offer the game industry in-depth insight to potential solutions that may not be apparent to people who have studied, but have not experienced disability firsthand.” AbleGamers’ Player Panels will connect disabled gamers and top organizations that share the mutual goal of making sure as many people as possible can game regardless of their disability. Player Panels team member qualifications only require a love of video games and some form of disability. Those approved will be compensated for their time and expertise. Gamers with disabilities who are interested in joining can sign up today at www.ablegamers.org/player-panels. View full story
  24. Hi, A fairly big wall of text here, sorry. I'm currently at the end of an internship to validate my Computer Science master degree, specialized in High Performance Computing. After my internship I wanted to leave France, to get a working experience somewhere in Europe. Unfortunately, it seems I don't really like the daily routine of this field. Now I'm wondering what to do with my future. I don't have any meaningful, game related, portfolio material as I preferred to spend my free time focusing on school project and some random Linux tinkering. After a quick look and some reading, it seems working on graphics/physics engine seems like a really interesting (also complicated) task. I've gathered a list of recommended books to read and practice on: some C++ books, some game engine/design books, some physics/maths book applied to 2D/3D computing, design pattern applied to game programming and other general game making related books. Now I can't just not look for work and focus on self-study for some years… and I doubt someone would hire with my current set of skills. I'm still young, I could try to follow another course about game making. I'm used to almost free university, so I'd prefer to not spend 10k in a private game making school. But is getting another degree even a good idea? I've always went from one course to the other, without putting too much thinking into it. But now I'm kind of lost about what to do, and it's eating me inside To give you a bit more background, here is what kind of skills I learned and practiced during my degree and my internships, sorted by how much I know in the field, somehow (a bit technical here): - Shared memory (threads POSIX, OpenMP) and distributed memory (MPI) computing - Inner mechanisms of past and modern Operating System: processes, threads, scheduling, memory management (address spaces, virtual memory, pagination, segmentation), study of classical synchronization problems - Computer architecture and hardware (cache, TLB, pipeline, hardware multithreading, …) - GPU Computing applied to HPC (CUDA, OpenMP, OpenACC, OpenCL) - Low level optimization techniques (vectorization, intrinsics, cache use, profiling, assembly…) - Non-blocking algorithm: use of hardware atomic primitives to synchronize threads without the use of locking mechanism - Parallel algorithmic (N-body approximation, load-balancing) - Some basic linear algebra (BLAS, dense and sparse LU facto) I think most of what I know isn't really what game companies would need anyway. I'm only really experienced with C but I know some others scripting languages. Since recently, I'm also learning C++ on my own free time. I've also had some general courses about software engineering. Any advice, recommendation, question, anything?
  25. Hello, My name is Hristo Kolev, a student at “Manchester Midi School”, Manchester, UK and I will be graduating this August with a degree in “Music production and audio engineering”. As part of my final research paper I am exploring the development of game audio through the years and the role of the composer as part of the development team. The research is mainly focused on the connection between audio and technological developments and the skills a musician has to have in order to work in the industry. I will be extremely grateful if you agree to answer few question on the topic. Name: Date: 1. How long have you been composing for video games? 2. What is the most effective platform of promotion for you as a composer? 3. What are the essential skills a game composer needs and how did you gain these skills? 4. What are the biggest challenges you have faced in becoming game audio professional? 5. How composing and sound design have changed over the years and how did you managed to adapt to those changes? 6. Do you think that in technological aspect game audio is reaching its limit for innovations? 7. With so many requirements today, such as composing, sound design, knowledge and understanding of scripts, programing and coding, Wwise and FMOD, how do you manage to learn everything and keep track of all new innovations and which of these you think are most essential for a young composer or audio engineer? Please feel free to add any addition information you find useful. Any advice will be highly appreciated! Kind regards, Hristo Kolev