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IFooBar

does Intel supports 3DNOW?

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IFooBar    906
I couldve sworn that some bit in the ecx register on a call to cpuid with eax = 1 indicated whether 3DNOW was available on an Intel processor! Though I was just going through the Intel CPUID sheet just now and I couldnt find anything for detecting 3DNOW on an intel processor. Does intel support 3DNOW? and if so, how do I detect it? thanks.

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Narcist    126
No its AMD only


Establish that the processor has support for CPUID.
Execute CPUID function 0, which returns the processor vendor string and the highest standard function supported. Save the vendor string for a later comparison. (See step 9.)
If step 2 indicates that the highest standard function is at least 1, execute CPUID function 1, which returns the standard feature flags in the EDX register.
If bit 23 of the standard feature flags is set to 1, MMX technology is supported. MMX instruction support is the basic minimum processor feature required to support other instruction extensions.
Optionally, if bit 25 of the standard feature flags is set, the processor has streaming SIMD extensions (SSE) capabilities. Further qualification of SSE is done by checking for OS support. SSE support might be present in the processor, but not usable due to a lack of OS support for the additional architected registers.
Execute CPUID extended function 8000_0000h. This function returns the highest extended function supported in EAX. If EAX=0, there is no support for extended functions.
If the highest extended function supported is at least 8000_0001h, execute CPUID function 8000_0001h. This function returns the extended feature flags in EDX.
If bit 31 of the extended feature flags is set to 1, the 3DNow! instructions are supported.
If the previously saved vendor string (see step 2) contains "AuthenticAMD", continue on to the next step.
If bit 30 of the extended feature flags is set to 1, the additions to the 3DNow! instruction set are supported.
If bit 22 of the extended feature flags is set to 1, the new multimedia enhancement instructions that augment the MMX instruction set are supported.


[edited by - Narcist on January 16, 2004 6:11:13 AM]

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IFooBar    906
quote:
Original post by Narcist
No its AMD only


If the highest extended function supported is at least 8000_0001h, execute CPUID function 8000_0001h. This function returns the extended feature flags in EDX.
If bit 31 of the extended feature flags is set to 1, the 3DNow! instructions are supported.
If the previously saved vendor string (see step 2) contains "AuthenticAMD", continue on to the next step.
If bit 30 of the extended feature flags is set to 1, the additions to the 3DNow! instruction set are supported.
If bit 22 of the extended feature flags is set to 1, the new multimedia enhancement instructions that augment the MMX instruction set are supported.



See the bold text. It says bit 31 in the extended flags shows 3DNOW support. But that is not only for AMD, because the underlined text would've been written beforethe bold text had it only been for AMD.

right? RIGHT?

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[edited by - ifoobar on January 16, 2004 7:09:16 AM]

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IFooBar    906
erm, heh... You win.

Though they should rewrite that bit of info you posted up there. AMD is misleading people. I think maybe for the last year I was under teh impression that 3DNOW was a standard!! All because of that sheet I saw somewhere before.

But you are absolutely sure that Intel has no 3DNOW support right? ..... RIGHT???

thanks for letting me know.

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Narcist    126
SSE is superior to 3dnow anyway, 3dnow works on 2 floats at a time, SSE works on 4 floats, the only nice bit of 3dnow is the newton raphson stuff for accurate recip, recip sqrt but you can do it in about the same time by hand on SSE anyway (see the intel docs on how to)

I * think the following is true, but i''m not so hot on the AMD aspects

k6/k6 and above from AMD has 3DNow!
althon and above from AMD has 3DNow! extensions
Athlon MP/XP and above from AMD has SSE aswell as 3dNow!

I *think* athlon and above also have MMX but i''m not sure

P-MMX and above from Intel has MMX
P-Pro and above from Intel has SSE
P-4 and above(?) from intel has SSE2

I know nothing about the 64bit cpus (itanium and the like) but i would guess that the fastest code on those will be their native code anyway.

Ideally, simply detect what is there using the method i described above and use what you can.

Eg if you detect SSE2 and you have code that can be most optimal using SSE2, use that code

if you detect SSE, then you can use SSE code

if you detect 3DNow!, then you can use 3DNow! code

if you dont detect any looks like your stuck with plain scaler math


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T2k    220
if i detect 3dnow and sse (and maybe sse2) can i use them at the same time? (2floats from 3dnow +4floats from sse =>6floats ?)


T2k

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samgzman    160
Even if you could run SSE2 and 3DNOW code together, you can''t run them in parallel straight up. So the point is defeated just go with SSE2.

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T2k    220
quote:
Original post by samgzman
Even if you could run SSE2 and 3DNOW code together, you can''t run them in parallel straight up. So the point is defeated just go with SSE2.


damn amd''S they need HT so one thread can use 3dnow and the other sse :D, erhm do pentiums with HT have 2 SSE2 paths? or do they have to share one SSE2?


T2k

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Jan Wassenberg    999
IFooBar: Intel has apparently adopted AMD''s extended CPUID convention, just to avoid conflict. No Intel CPU I know of has 3DNow! - pity.

Narcist:
> SSE is superior to 3dnow anyway, 3dnow works on 2 floats at a time, SSE works on 4 floats
I prefer 3DNow - nicer instructions, and 4 floats/op is usually ''too big'' (4.4 dot product, the first multiply is great, then you''re just shuffling stuff around).

SSE/3DNow processor support is correct, except SSE - that''s only available on the Intel side starting with PIII. The problem with runtime conditional code is that it carries some overhead with it. Best to rewrite the whole algorithm in 3DNow, vs. splitting at the sqrt / dotproduct level.

> if i detect 3dnow and sse (and maybe sse2) can i use them at the same time?
Yes! I did this in my CLOD refine code (crazy-optimized), because of course 8 registers wasn''t enough. You still have the limit of one fadd and 1 fmul op / clock though.

HT CPUs share execution resources (hoping that one ''processor'' is not using all of them) - this hurts optimized code, obviously.

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