DOD and memory layout

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31 comments, last by Yuukan 12 years, 3 months ago
OP has shown using SoA, and from two other posters I've seen the answer is to better use AoS. Now, granted that the idea is to clump data together, don't these other non-desktop-pc devices still typically have more than 1 cache line? As well as some sort of SIMD instructions?

Why is the advice for Data-Oriented-Design to use AoS then, assuming (incorrectly maybe?) that the above is true?
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I'm not sure about non-pc devices, but pc's map cache lines to memory in such a way that multiple areas of memory are mapped to the same cache line. If you have an SoA with say 2000 elements in each array, the memory containing positions[ id ] and speeds[ id ] could map to the same cache line, meaning each operation could potentially cause 2 cache misses each time.

Contiguous areas of memory, however, are going to be mapped to different cache lines, so AoS provides a much smoother memory usage pattern, especially when the processor preloads memory into cache. While working on cache line 1, cache line 2 will be loading and so on.

I'd look at it as a velocity / position update.

What would you do if you need the position data in another component with this system?

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