Hi
I am looking to perform MIMD operation on SIMD architecture?
Can I do this?
1 Vector unit -> (4) + (4)
2 Vector unit -> (4*6) + (4)
instead of doing
1 Vector unit -> (4) + (4)
2 Vector unit -> (6) + (4)
And If I can do this, both of them will take same amount of time?
If all you got is one processor, then no.
I am looking to perform MIMD operation on SIMD architecture?
If all you got is one processor, then no.
I am looking to perform MIMD operation on SIMD architecture?
http://en.wikipedia.org/wiki/MIMD
Can it be done with some sort of hack?
Can it be done with some sort of hack?
Can it be done with some sort of hack?
No, but you can use a 1, in this case:
(4*1) + 4
(4*6) + 1
Will it be done in same amount of time as
4 + 4
24 + 4
Do superscalar CPUs count as MIMD? Why is this important? How does such example map to real world?
I think there was never hardware that executes real MIMD. Some stream processors support that kind of, they use VLIW and execute different operations on every register lane, but the instruction streams are always interleaved in one real stream, hence there can be no diverging branching.
The latest PowerVR Rogue architecture might be close -- given applicability to OP, this is a bit of a non-sequiter -- but its real silicon, and a non-SIMD GPU that can actually do divergent branching as I understand it.
For what its worth, I suspect that when we see real implementations, low-power applications will be where we do (the Rogue GPU is a mobile-focused part). From a power-savings perspective, avoiding power-waste due to executing both sides of a divergent branch and then reconciling results is wasteful of battery and generates heat needlessly.
